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Test Number : PMP
Test Name : Project Management Professional - PMP (PMBOK 6th Edition)
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PMP exam Format | PMP Course Contents | PMP Course Outline | PMP exam Syllabus | PMP exam Objectives

Analytical skills
=> Benefit analysis techniques
=> Elements of a project charter
=> Estimation tools and techniques
=> Strategic management
=> Change management planning
=> Cost management planning, including project budgeting tools and techniques
=> Communications planning
=> Contract types and selection criteria
=> Estimation tools and techniques
=> Human resource planning
=> Lean and efficiency principles
=> Procurement planning
=> Quality management planning
=> Requirements gathering techniques (e.g., planning sessions, brainstorming, and focus groups)
=> Regulatory and environmental impacts assessment planning
=> Risk management planning
=> Scope deconstruction (e.g., WBS, Scope backlog) tools and techniques
=> Scope management planning
=> Stakeholder management planning
=> Time management planning, including scheduling tools and techniques
=> Workflow diagramming techniques

Continuous improvement processes
=> Contract management techniques
=> Elements of a statement of work
=> Interdependencies among project elements
=> Project budgeting tools and techniques
=> Quality standard tools
=> Vendor management techniques

Performance measurement and tracking techniques (e.g., EV, CPM, PERT, Trend Analysis)
=> Process analysis techniques (e.g., LEAN, Kanban, Six Sigma)
=> Project control limits (e.g., thresholds, tolerance)
=> Project finance principles
=> Project monitoring tools and techniques
=> Project quality best practices and standards (e.g., ISO, BS, CMMI, IEEE)
=> Quality measurement tools (e.g., statistical sampling, control charts, flowcharting, inspection, assessment)
=> Risk identification and analysis techniques
=> Risk response techniques
=> Quality validation and verification techniques

Archiving practices and statutes
=> Compliance (statute/organization)
=> Contract closure requirements
=> Close-out procedures
=> Feedback techniques
=> Performance measurement techniques (KPI and key success factors)
=> Project review techniques
=> Transition planning technique

Active listening
=> Applicable laws and regulations
=> Benefits realization
=> Brainstorming techniques
=> Business acumen
=> Change management techniques
=> Coaching, mentoring, training, and motivational techniques
=> Communication channels, tools, techniques, and methods
=> Configuration management
=> Conflict resolution
=> Customer satisfaction metrics
=> Data gathering techniques
=> Decision making
=> Delegation techniques
=> Diversity and cultural sensitivity
=> Emotional intelligence
=> Expert judgment technique
=> Facilitation
=> Generational sensitivity and diversity
=> Information management tools, techniques, and methods
=> Interpersonal skills
=> Knowledge management
=> Leadership tools, techniques, and skills
=> Lessons learned management techniques
=> Meeting management techniques
=> Negotiating and influencing techniques and skills Organizational and operational awareness
=> Peer-review processes
=> Presentation tools and techniques
=> Prioritization/time management
=> Problem-solving tools and techniques
=> Project finance principles
=> Quality assurance and control techniques
=> Relationship management
=> Risk assessment techniques
=> Situational awareness
=> Stakeholder management techniques
=> Team-building techniques
=> Virtual/remote team management

1. Initiating 13%
2. Planning 24%
3. Executing 31%
4. Monitoring and Controlling 25%
5. Closing 7%
Total Number of Scored Questions 175
Total Number of Unscored (Pretest) Questions 25
Total Number of Questions 200

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SPIRIT IP-XACT managed ESL Design device applied to a community-on-Chip Platform | PMP real questions and Latest Questions

Emmanuel Vaumorin and Maxime Palus, Magillem Design ServicesFabien Clermidy and Jérôme Martin, CEA Leti – Minatec


community-on-Chip is a extremely lively field of research of the fresh years. compared to classical bus-primarily based verbal exchange schemes, it implies ingenious mechanisms in addition to new methods of wrapping intellectual homes, giving greater verbal exchange capabilities. To take care of the equipment design complexity, stronger electronic device level design environments are vital. The goal of this paper is to evaluate the merits of an IP-XACT based environment utilized to community-on-Chip design. They show the level of automation achieved within the design stream, discuss its efficiency for the design and verification steps, and propose advancements.


community-on-Chip (NoC) platforms are an alternative to the standard bus architectures [2]. providing a verbal exchange-centric method of a design, they goal at overcoming the limitations of buses because of an improved wire efficiency and a help for new conversation-centric schemes [4]. because of the NoC paradigm, both the design and utility mapping are claimed to be simplified.

besides the fact that children, before this dream becomes true, efficient strategies for NoC implementation must be set-up. certainly, NoC architectures handle advanced techniques on Chip (SoC), which might be enclose dozens of IP cores. consider probably the most appropriate NoC topology, plug the IP cores on it, simulate and validate the performances of the received design, and probably exchange IP cores’ relative positions on the NoC to increase efficiency, are average challenges met with the aid of a NoC-based mostly SoC clothier. in an effort to handle this complexity and discover the knowledge design space at good value time and effort, committed tools should be used.

numerous solutions are proposed in the literature. The Polaris framework [8] presents a complete development chain including equipment for software site visitors modeling, excessive-degree design exploration, and backend-stage projections and validations. Its design-space exploration performs on the NoC topology and on its quality of provider (QoS). an analogous tool suite has also been exhibited for the ×pipes architecture [7], together with NoC synthesis and know-how projection. As regards the Ætheral architecture [3], its associated equipment offer monitoring features for debug.

during this paper, they believe the FAUST2 platform, sequel of the FAUST one [5]. It proposes an information streaming verbal exchange model to assure the homogeneity of records switch administration for all IP cores. An adaptable Configuration and conversation controller (CC) ensures the interfacing between IP cores and the NoC. unlike the NoC options offered above, where the representations of IPs are tool-particular, the chosen method to address the complexity of FAUST2 NoC design, and enrich the time to validation, become to use a common and unified representation of the total gadget to ensure assistance consistency at each level of the design flow. The point become to comfy the error-susceptible operation of rewriting the outline of a single IP for distinctive purposes, which commonly ends up in mismatch between the diverse models.

The IP-XACT average for IP description [9] goals at offering SoC designers with such a unified mannequin. it's an XML primarily based open average supposed to target the wants of industry, described via the SPIRIT consortium. This non-earnings corporation offers a unified set of necessities for documenting IPs using meta-data. These meta-data can then be used for configuring, integrating, and verifying IPs in advanced SoC design and interfacing tools the usage of normalized APIs. They will also be used to access design meta-records descriptions of complete techniques.

To consider the benefits that IP-XACT might convey to FAUST2- based SoC design, an IP-XACT compliant toolset known as Magillem has been chosen. Magillem supports superior functionalities defined by means of the normal, just like the capacity to run code turbines according to IP-XACT APIs, and amenities like a graphical design editor, tooling for IP import and packaging, design assembly and stream control.

The FAUST2 NoC platform is unique within the next section. The leading configuration parameters are extracted in an effort to element out the design complexity. section three indicates how IP-XACT will also be used to installation and manage an entire ESL circulation according to a 4-step method: library packaging, design assembly and verification, flow manage, and advanced circulate structure. area four then gifts the work realized to adapt and customise the Magillem framework to the FAUST2 NoC platform. eventually, bought effects and boundaries, in addition to future viable extensions of the movement, are discussed.


The FAUST2 network-on-Chip architecture buddies to every IP core an entire communique and Configuration controller (CC) (figure 1). This section describes its leading aspects. Flexibility of the proposed architecture is highlighted, and the ESL circulation requirements are deduced.

figure 1. IP integration in the FAUST2 NoC.

2.1 CC Overview

figure 2. conversation Controller overview.

determine 2 indicates a typical illustration of a CC. 4 components may also be distinguished, each fabricated from a couple of subcomponents with potent interactions between them:

  • verbal exchange management, together with circulate control, QoS, in addition to conversation scheduling facets, permitting disbursed conversation administration.

  • CC core configuration administration is in a position to deal with no longer simplest static or off-line configuration, however additionally dynamic: a configuration can be loaded interior the IP core best when mandatory.

  • test & Debug facets, offered by means of a check wrapper and through runtime traces and dump mechanisms, that permit genuine manage of an utility’s growth.

  • 2.2 Core/CC Interface

    To be related to a CC, an IP core has to healthy the interface shown figure three. This interface consists of a classical tackle/records configuration port, inputs and outputs for information flows, execution/reputation indicators to delivery and handle computation inside the IP core, and a few subsidiary alerts, e.g. for check functions. as much as four cores may also be linked to a single CC, which without doubt impacts the CC: it modifies the number of enter and output flows, and additionally some inside services. at last, the wiring between CC’s blocks is also impacted.

    additionally, and depending on the IP core (essential hardwired features up to complicated reconfigurable cores), some interface alerts may also be neglected and the width of some others may also be modified. for example, BIST alerts are indispensable in case of memory blocks presence, whereas size_released’s width depends upon the core administration of its memory and can range a lot from one core to a different.

    determine 3. CC and core interface.

    2.three verbal exchange & movement manage aspects

    aside from classical elements of a community interface (e.g. message constructing, stream manage and QoS), the CC provides an superior integrated verbal exchange scheduler. The communications as well as their sequence, are interpreted and performed via the CC, so that complex operations can be performed with out the need of intermediate reconfigurations by using an external controller, e.g. a CPU core.

    reckoning on the IP core, the CC can manage up to four input and 4 output flows, which modifies the number of blocks of the CC (e.g. numbers of OCCs, see determine 2). The number of configurations, as smartly as the complexity of the scheduling, are strongly based on each the IP core and its use within the finished SoC: the equal IP core may well be associated with distinct CCs, reckoning on the functions it realizes in the application flow.

    2.four Reconfiguration coping with

    The downsides of a versatile conversation controller are (1) an IP core may must be reconfigured right through a conversation sequence, as a way to understand the international applicative sequence and (2) the variety of required configurations, either for communications or for IP cores, could be very small or rather huge. To clear up the primary element, a scheduler of IP core configurations, that supports the equal sequences as for communications, is integrated within the CC. The 2nd element raises the equal problem of configurations storing for IP core as for the communications, as a way to play an entire sequence. depending on both the variety of core registers to configure and the number of diverse configurations essential, the necessary memory could be massive, or in the contrary very small. The FAUST2 method to resolve this problem consists in a configuration cache mechanism, the CC and the IP core are in a position to shop one or a number of configurations, and when a cache-leave out occurs, i.e. a mandatory configuration is not stored locally; the CC is in a position to automatically request it to a specialized IP core.

    The cache size of the core and the corresponding control are hence configurable. Core’s multiple configurations are handled via a slotid sign (see determine three) which is an non-compulsory characteristic.

    2.5 ESL circulation requirements

    As confirmed above, the particularity of the CC resides in its high level of flexibility: the variety of cores and enter/output flows, the verbal exchange and configuration complexity, and examine capabilities are examples of aspects which may also be set at designtime to be sure a perfect matching between the IP, the capabilities of its linked CC and utility-level necessities. Such an strategy avoids over-sizing of conversation-committed add-ons, saves vigor and improves performance. The counterpart is the need to have a extremely able and versatile design atmosphere. excessive-stage descriptions, akin to SystemC/TLM1 [6] need to also be supported in order to speed up the simulation of complex programs.

    From a NoC generation element of view, the requirements of a design go well with are: (1) to contend with optional signals and blocks, (2) to help distinctive widths for a sign, (three) to be in a position to modify the parameters of each and every CC subcomponent, and in certain cases to generate distinct capabilities for a same block, (four) to connect the subblocks to attain the proper CC, (5) to handle distinctive representations of a identical part and (6) to permit the remaining integration of the considered components in a complete design. In other phrases, the device suite has to be capable of offer an efficient access to all of the design parameters and features, and to have a unified illustration for all of the models describing the blocks. The subsequent part items the IP-XACT general, which is theoretically capable of fulfill the discussed pursuits. area four relates the experience of an IP-XACT-based design stream for the FAUST2 NoC platform.


    3.1 Overview

    IP-XACT from the SPIRIT consortium is these days diagnosed by using the electronics group as an apposite choice for managing adequately and efficiently the new ESL design flows [1]. having said that, the migration from a legacy design circulation to one other taking full advantages of IP-XACT requires some heavy and sophisticated operations. figure four presents the four steps which need to be completed. they are designated in here subsections.

    3.2 IP Description

    The intention of this primary step is to kit all of the accessories of an IP library into XML info in keeping with the IP-XACT schema, which describes the syntax and semantic guidelines for the outline of three sorts of facets: the bus definitions, the components and the designs (during which components are instantiated). thus the intention of the IP packaging is to fill in for every element the XML fields that describe its attributes: physical ports, interfaces, parameters, generics, register map, physical attributes, etc. an important part of the schema is dedicated to referencing the info regarding the diverse views of a component: a view can be for instance a simulable model in a specific language (VHDL, Verilog, SystemC, and so forth) or documentation data (e.g. PDF, HTML, Framemaker). This work enables future reuse of latest components, because all of their aspects are with no trouble accessible for its integration and configuration in an even bigger device, as it can be explained in the next step.

    determine four. A four-step methodology to build ESL flows.

    three.three gadget Description and Verification

    After the packaging step, is it viable to import, configure and integrate components into the gadget, assemble the design, get to the bottom of connections concerns, and automate design initiatives, hence lightening the verification steps. Some instance of the use of IP-XACT at this degree are:

  • Partial or full automation of design assembly and configuration, through TGI2-based generators that can instantiate, configure and fasten accessories in line with chosen design parameters (e.g. abstraction stages of components, type of structure, and so forth.).

  • Detection of conversation protocols mismatch, due to the bus interface management, with feasible insertion of the required adaptors/transactors.

  • era by way of a TGI generator of the finished netlist defined by way of an IP-XACT design, e.g. in SystemC or VHDL.

  • automated customization of compilation and simulation of designs. indeed a part’s description includes its whole linked file course for every of its views (TLM, RTL, and so forth.), so a generator may additionally construct makefiles, apply potential componentspecific compilation tags, and launch the compiler or simulator with the acceptable command line.

  • three.four circulate control

    The third step of the methodology, depicted within the subsequent figure, goals at linking the design actions across the centric IP-XACT database through capacity of a dedicated ambiance which gives entry to the IP-XACT tips. The Magillem device provides an IP Packager, a Platform meeting device, in addition to a Generator Studio to strengthen and debug further TGI-based mostly turbines. These may be encapsulated in the IP-XACT illustration of an IP and may as an instance effectively launch the execution of a script, getting arguments values from the design description in IP-XACT, or be on the contrary a greater complex engine, the position of which might be to modify the design itself (e.g. add connections, insert adapters, or configure accessories).

    determine 5. precept diagram for an IP-XACT circulate.

    Checkers can even be developed and used to determine design rules at some aspect, before going extra within the design flow. anyway, IP-XACT gives mechanisms to describe the sequences of chained mills and checkers.

    3.5 superior movement structure

    This last step in the methodology has a high skills because it exploits all features described up to now and allows the precise implementation of advanced ESL actions, equivalent to architecture exploration or software application automatic mapping on a hardware platform. These instance show the complexity that needs to be managed via the three first steps: all add-ons must be packaged and their configurability must be taken under consideration; the design meeting automation should be maximized, while any structure choice should be dealt with. ultimately, the generator chains, as defined up to now, may also be configured and managed through supervisor engines: as an example a validation sequence will configure and execute a number of instances the generators dedicated to testbench configuration, compilation and simulation.

    4.IP-XACT move utilized TO FAUST2

    four.1 Presentation of the ESL Design circulation

    The evaluation of the design circulate used for the FAUST2 platform (IPs, equipment, methodologies, documentation, and so forth) has led to the definition of five actions to be install for the committed IP-XACT stream, introduced in figure 6 and distinct hereafter.

  • project administration: description of the undertaking’s folder constitution, course place of equipment, venture’s parameters administration.

  • IP-XACT packaging of the library: extraction of IP information in folder structure and creation of metadata information.

  • NoC assembly: technology of the contraptions’ interfaces, generation of the network, configuration of the routers.

  • Compilation: environment of parameters, creation of compilation initiatives (makefiles) taking in account the context (TLM/RTL languages), compilers execution.

  • Simulation & efficiency evaluation: parameters interface, management of a simulation assignment, launch of simulations, extraction of effects and returned annotation in IP-XACT for evaluation.

  • figure 6. ESL design move for FAUST2.

    4.2 IP-XACT Packaging of the TLM and RTL components

    The packaging process begins with the definition of the verbal exchange protocols between modules. That capability that agencies of physical ports which belong to a equal protocol are defined (IP-XACT busDefinition object). The path of each port is precise for a target (slave) and for a supply (grasp) use of the considered protocol. any other advice can also be kept, like the width of a port, default values, timing constraints, and so forth. These busDefinitions were created manually for the FAUST2 platform using the Magillem integrated IP-XACT editor. concerning the packaging of the interfaces of RTL accessories to create their IP-XACT illustration, it has been immediately executed through Magillem with a parsing system able to extract the assistance from the VHDL mannequin information. For the TLM components, this step has been finished with the IP-XACT editor, which has also been used to update the representations with complementary assistance like register representation, IP-XACT generator inclusion, definition of selected parameters, and many others. After the packaging step, the IP-XACT components can also be instantiated and linked in a graphical editor to create comprehensive techniques or hierarchical add-ons.

    4.three CC computerized technology

    The FAUST2 CC, added in section 2, is product of 13 submodules with a high degree of parameterization: variety of cores interfaced by using the considered CC, number of statistics inputs and outputs, configuration reminiscence measurement, core popularity sign width, and many others. These parameters enable the tuning of the CC to healthy the wants of the connected cores. in the leisure of the paper, the time period “certain” qualifies a part that has been configured according to the parameters chosen through the clothier, as adversarial to a “accepted” aspect.

    The complete CC generation procedure is dealt with through Magillem. An IP-XACT description of a accepted CC, with the minimal interface, has been created, which encloses a generator capable of create a selected CC. universal IP-XACT accessories have also been created for all of the submodules of the CC. They contain the interface, the memory map and a generator to create the corresponding specific CC submodule.

    The era of a specific CC is the effect of the execution of a group of generators written in Java (counting on an extension of the IP-XACT TGI API) and Perl languages. The prolonged API provides Magillem specific functions like VHDL netlisting of an IP-XACT design and graphical manipulation of design representations (situations and ports region and colours, selected trademarks for add-ons), and so forth.

    first off, a frequent CC is instantiated in a design and its embedded generator is known as. This generator creates each the IP-XACT and VHDL descriptions of the specific CC, matching the chosen design parameters. As regards the IP-XACT mannequin, tips in regards to the interface, the reminiscence map and the VHDL model file set are captured in an IP-XACT part, whereas structural tips (subcomponents, connections) are captured in an IP-XACT design.

    each submodule of the certain CC is then generated with the aid of instantiating the corresponding popular submodule in the CC design and operating its embedded generator, which performs the following operations:

  • advent of the selected IP-XACT submodule.

  • call of a Perl generator which uses a widespread template of VHDL code to creates the selected submodule’s RTL model.

  • Substitution of the commonplace IP-XACT part with the generated particular one.

  • Then the connections between submodules and to external ports are introduced to the CC design, and the world CC reminiscence map and file set are created with the aid of gathering the counsel in all particular submodules, thereby completing the IP-XACT mannequin of the particular CC. determine 7 suggests a completely-generated IP-XACT design because it seems on the conclusion of this procedure.

    figure 7. Graphical view of the IP-XACT design of a CC.

    at last the VHDL representation of the comprehensive CC is automatically generated by using the device, which assembles the prior to now created selected VHDL add-ons.

    four.four Design assembly Automation

    The CC generation isn't the simplest automation provided by the use of IP-XACT equipment and turbines applied to the FAUST2 platform. one other TGI generator allows encapsulating and developing IP-XACT views of each SystemC/TLM and VHDL models of the good design of an entire FAUST2-based mostly SoC. It uses a textual content configuration file that includes the desired topology of the NoC interconnect and the identify of IP cores that should still be plugged on it. The SystemC/TLM model of the NoC is created on the identical time by way of an exterior generator, along with a set of configuration data used to application and verify the described SoC. besides, a VHDL netlister makes it possible for to get the corresponding RTL model of the whole SoC in a simple push-button manner.

    The same correct design technology mechanism is used to create TLM/SystemC simulation testbenches by adding or changing some IP cores by way of debug-specific SystemC gadgets. The person may additionally additionally decide to simulate each and every regarded IP core at TLM or RTL stage, relying on exterior co-simulation tools.

    figure 8. View of the IP-XACT design of a 3x3 NoC.

    5. assessment AND dialogue

    5.1 benefits for the FAUST2 Design movement

    The IP-XACT ESL design circulate introduced within the previous part has been Tested so as to create a considerable number of testbenches of FAUST2- based mostly programs. The main merits stated all the way through these assessments are the ease of use, the unified model that references all assistance on the design accessories, and the reduced extend between the choice of the parameters and the finished meeting of the design.

    Ease of use emphasizes the want of effective IP-XACT tools such because the Magillem suite, which offers graphical representation and manipulation of IP-XACT fashions, hiding the verbosity of XML description info. From a fashion designer aspect of view, it makes it possible for to flick thru the design hierarchy to locate and replace any critical tips. moreover, mills will also be run during the graphical person interface, and their effects instantly considered in the tool. The automation percentages, via configuration information, scripts and turbines, additionally enables to disguise the complexity of operations to the conclusion consumer: when producing a CC for a core, he only has to enter the chosen parameters and get a complete CC after a couple of seconds.

    The purpose of having a unified model that references all tips concerning the add-ons of a platform is to evade redundancy of counsel between databases: it is fairly normal, for a SoC fashion designer, to use distinctive equipment from a lot of CAD companies, each and every one dealing with specific counsel stored in distinctive formats. In such cases it's complex to be certain the consistency of the guidance, because when modifying some facts used via one tool you probably have to exchange the facts used by different tools, this being a usually error-inclined operation. IP-XACT presents the chance to instantly replicate a transformation on all thinking suggestions.

    at last, the checks confirmed an important discount in the design to validation cycle time. certainly, when a brand new IP core has been developed in accordance to the FAUST2 core interface layout proven in determine 3, it handiest takes a couple of minutes to import it and acquire its CC for a given set of parameters. Getting a complete testbench the use of this IP plugged on a NoC is also a depend of minutes. The fashion designer might also hence concentrate on genuine valueadding tasks, like picking architectural houses (NoC topology, memory size, multithreading help) and simulate the generated design to consider the performances. This enables a bigger design house exploration than a manual parameterization of the testbench.

    youngsters the use of IP-XACT for the FAUST2 platform has additionally showed some boundaries or weaker aspects which might be introduced within the subsequent subsection.

    5.2 boundaries

    essentially the most glaring drawback of adding IP-XACT to an ESL design circulation is that it requires learning the IP-XACT format, integrating it into the prior to now used design database and packaging all used IPs. however this best needs to be performed as soon as, the latter step might also take a considerable period of time, especially for complicated methods. indeed no longer all information could be taken under consideration through automatic packagers, and many of the time some facts, e.g. handle mapping assistance, should be crammed in manually.

    Of course IP-XACT mills even have required a few months to be developed and tuned to the particular wants of the FAUST2 platform, with a purpose to obtain this sort of degree of design automation. even so, frequently used commercial CAD equipment do not currently assist IP-XACT natively. This skill that, to make certain an accurate and automated transmission of design facts to and from these tools, certain generators need to be developed and debugged.

    5.3 perspectives

    The assessment of IP-XACT talents advantages for the FAUST2 design move should be pursued. the two main foreseen advancements contend with the hyperlink of the unified model with backend tools and with the embedded application building on the FAUST2 platform.

    A link with backend tools would carry the possibility to reflect in the unified model some qualities calculated by using the equipment. as an example, for a given core, power consumption to comprehend regular operations, and optimum computing performance, can be stored in the unified model, and used by high degree TLM/SystemC models of a complete device to have useful energy and efficiency estimation for a complete utility running on a SoC.

    From the embedded utility design factor of view, the unified model already consists of lots of important counsel, above all involving address mapping. A generator might effectively clear up the error-prone manner of rewriting the tackle map in keeping with the syntax of chosen programming language, in addition to mirror immediately in utility any trade within the hardware tackle map.


    during this paper, they showed how an IP-XACT-managed ESL design circulate may additionally tackle the design complexity of NoC-based mostly SoCs. This normal offers a unified illustration of all primary design tips. within the general FAUST2 case, it permits a brief integration of an IP core inside the design, in addition to an automatic generation of finished methods.

    although, the can charge of switching from legacy to IP-XACT flows is not negligible, as it commonly requires guide operations to get a complete description of IPs. additionally, native IP-XACT assist by current design equipment is totally appealing, as for now mills ought to be written to transfer relevant records to the CAD equipment. as soon as these two aspects are solved, IP-XACT flexibility provides the designers with very beneficial design flow customization and automation facilities.


    [1] Bailey, B., Martin, G. and Piziali, A. 2007. ESL Design Verification. Morgan Kaufmann Publishers, 2007

    [2] Benini, L. and De Micheli, G. 2002. Networks on Chips: a new SoC Paradigm. IEEE Transactions on computer systems 35, 1, (Jan. 2002), 70-seventy eight.

    [3] Ciordas, C., Hansson, A., Goossens, okay., and Basten, T. 2006. A Monitoring-mindful network-on-Chip Design movement. In complaints of the 9th EUROMICRO conference on Digital equipment Design. DSD '2006.

    [4] Henkel, J., Wolf, W., and Chakradhar, S. 2004. On-chip networks: a scalable, communication-centric embedded gadget design paradigm. In court cases of the seventeenth foreign convention on VLSI Design (June 21 - 24, 2004), 845 - 851.VLSID '04.

    [5] Lattard, D., et al. 2007. A Telecom Baseband Circuit in line with an Asynchronous NoC. In IEEE international strong-State Circuits convention Dig. Tech. Papers (Feb. 11 - 15, 2007), 258 - 601. ISSCC '07.

    [6] Open SystemC Initiative (OSCI) homepage.

    [7] Pullini, A. et al. 2007. NoC Design and Implementation in 65nm technology. In proceedings of the primary international Symposium on community-on-Chip. NOCS '2007.

    [8] Soteriou, V., Eisley, N., Wang, H., Li, B., and Peh, L. S. 2007. Polaris: A equipment-degree Roadmapping Toolchain for On-Chip Interconnection Networks. IEEE Transactions On Very big Scale Integration (VLSI) methods 15, 8 (Aug. 2007), 855 - 868.

    [9] SPIRIT Consortium homepage.

    1 TLM: Transaction level Modelling.

    2 TGI: Tight Generator Interface is the identify of the API defined by means of SPIRIT for having access to facts kept in an IP-XACT database.

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