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a good ASIP Design Methodology | 000-275 PDF Braindumps and PDF Dumps

Selim ZOGHLAMI*, Raphael DAVID*, Stéphane GUYETANT* and Daniel ETIEMBLE*** CEA listing, Embedded Computing Laboratory** LRI - laptop Science Lab

abstract :

The processors that are used in embedded techniques ought to fulfil a collection of constraints: software execution time, power consumption, chip size, code size and so forth. during this paper, they focal point on the design of utility certain guideline-set processors, and more exactly on a good methodology for the Design house Exploration of an ASIP for the audio and speech area. the use of this methodology, they designed a excessive performance ASIP reaching over 13GOPS/mm2 with a 350MHz clock frequency in a low-power 65-nm TSMC technology. The development time was less than two man-months.

1. CONTEXT

The Design area Exploration of an ASIP (software specific guide-set Processor) can also be very complex because of the large number of design parameters. In their design case examine, they center of attention best on some key architectural features like the pipeline depth, the variety of registers, the implementation of special operations, the variety of guidelines that can be achieved concurrently etc. finding the highest quality exchange-off for the values of all these parameters isn't obvious and they need a selected design methodology to satisfy all necessities.

In determine 1, they present distinctive tactics that can also be used to locate the most appropriate change-off. To make the figure readable, they handiest use accept as true with two design parameters P1 and P2 that may well be as an instance pipeline depth and the number of guidelines that are carried out concurrently.

figure 1: different tactics to discover the optimum values of two design parameters

(a) The exhaustive search considers the entire possible values of every parameter. Due the massive variety of parameters, it is infeasible to evaluate each and every aspect of the design house and compare it to all of the other ones. Heuristic search techniques may still be used leading to suboptimal answer.

(b) to be able to evade that an heuristic search stops the hunt at a native most reliable, a 2nd approach known as random sampling is introduced here. It consists in picking randomly the couples of parameters but again there is not any warranty to converge towards an acceptable outcome.

(c) With the guided-search method, the clothier begins with a preliminary alternative of two parameters, and iterates round step by step except finding an acceptable alternate-off. This method avoids inconsistent or conflicting values for the distinct parameters and represents the ultimate design solution when the entry factor is neatly chosen.

(d) Many other strategies may even be considered, as using genetic algorithms, computer discovering based mostly searches, and the like.

For their design, they use the guided search of parameters. First, they examine the most important aspects of their architecture. Then, they use a design device to quantify these distinctive points and the rest of the architecture. So what they suggest here is a design methodology in line with a guided-search of parameters. The paper will continue with the presentation of that design methodology, then the architecture is special. The results and the validation consequences of the designed processor follow. and finally, further works are delivered.

2. DESIGN METHODOLOGY

Our goal is to discover a superb exchange-off between the time-todesign and the performances of an ASIP for a particular utility area.

2.1 Their benchmarks

For their case examine, they choose the Audio and Speech requirements as a selected and mostly used area of embedded systems. a number of audio and speech requisites with different encoding options are available, from lossless to lossy coding. desk 1 summarizes the set of benchmarks that they used for the Audio ASIP Design. each one of these benchmarks come from MediaBench. They cowl each distinct coding concepts and a few key points like bit-prices and computing complexities. greater particulars on audio coding ideas are given in [1], [2], [3] and [4].

desk 1: Audio purposes Benchmark

2.2 Benchmark Profiling and Analysing

The selected benchmarks were profiled the use of GPROF [5], the general public GNU profiler. The outputs of the profiler supply the name graphs and the hotspots, i.e. essentially the most time consuming features. For their audio-speech benchmarks, they recognized 14 hotspot capabilities such as the codebook most effective parameters filter search from the CELP (Code Excited Linear Prediction) regular or the MP3 (Mpeg-1 audio- part three- layer three) Modified Discrete Cosine transform. those hotspots take over sixty six% of average execution time. With these evaluation of the hotspots, they cover all audio wants. Their restrained quantity makes the guide evaluation feasible. The hotspots can even be analysed to assess the architectural aspects that could accelerate the execution. for example, they will identify the register and storage needs, the statistics-direction widths, and so on. for example, desk 2 gifts the number of registers that might be mandatory for a good execution of each and every audio-speech hotspot. These wants had been recognized from the comparison of the lifestyles period of variables within the execution graph.

table 2: Estimated registers wants of audio-speech hotspots

we've additionally identified some selected code points that may be accelerated by way of specific hardware features reminiscent of a pre-arithmetic shift. Their benchmarks also intensively use loops for which optimizing each loop conditional branches and computation conditional branches is simple.

2.three structure Sizing

2.3.1 simple assumptions for the initial edition of the structure

The initial version of the architecture that they used is now offered. It makes use of a customary RISC (reduced guideline- Set computing device) guideline set architecture with 1-guide delayed branches, conditional code flags (CC flags) for conditional branches (like the SPARC ISA). The ISA (guide- Set structure) is implemented both with a regular 5-stage pipeline for the scalar version and the n-manner superscalar or VLIW (Very long guide observe) models. Some points in the reduction of the variety of completed instructions each for the scalar or n-method types. The number of CC flags is any such function it truly is presented within the next part. an extra basic feature is the variety of guidelines that the hardware can execute concurrently, i.e. the value of n for the n-way approach. It will be mentioned in a subsequent part.

2.3.2 Conditional Codes Flags Sizing

As up to now mentioned, loops are normal in their benchmarks and that they combine a loop branch and one (or several) computation branch within the loop. often, the outcome of a complete loop computation is scaled on the end of the loop. So they need a flag for the loop branch and one more one for the conditional result scaling. Having one or a number of CC flags affects on the normal performance of the loop.

table 3: assessment of Conditional Codes Flags Implementation

within the example shown within the table three, enforcing two diverse CC flags saves one cycle by using loop new release. With just one CC flag, there is no strategy to fill up the extend slot after the loop branch, as the CMOV instruction must comply with the first SUBCC whereas the JMP CC ought to comply with the second example of the SUBCC. With two distinct CC flags, the CMOV guide can be moved into the branch delay slot eliminating the NOP that became necessary in the previous case.

The benefit can all of a sudden grows with n-way architectures. during this situation, the loop department circumstance SUBCC1 may also be evaluated within the equal cycle as another guide. In table 4, with a 2-method structure, they keep an additional cycle per generation.

desk 4: evaluation of Conditional Codes Flags Implementation for a 2-ILP architecture

The have an effect on of the number of CC flags may also be evaluated by using a metric called ”guide utilization rate (IUR)”, that is described because the number of positive instructions over the basic variety of directions (that comprises effective and NOP guidelines). This guide utilization fee can also be described as 1−NOPpercentage. In desk 4, if the first M instructions completely outfitted on the structure resulting in N/2 cycles and zero NOP, an evaluation of that metric for each implementations ends up in:

using several conditional codes flags increases the efficiency and it more efficaciously uses the capabilities of the architecture. The chip enviornment cost is relatively small and there's no problem for the instruction-set coding. obviously, the effects that are shown in desk 4 are in response to an easy 5-stage pipeline just like the MIPS-R2000 one [6]. Deeper pipelines may lead to other effects. for example, the pipeline of Alpha 21164 [7] had 2 execution levels (EX1 and EX2): the comparison of the situation was achieved all over EX1 stage, whereas the conditional department became performed all through EX2. in that case, each the guide setting the circumstance and the conditional department can be scheduled in the same clock cycle getting rid of a lot of NOP instructions in desk 4. using deeper pipelines may be considered in additional works.

2.3.three N-approach architectures

The purpose of the article is to latest a design methodology in response to a driving parameter well chosen. They focal point on the variety of executions to be executed simultaneously because the driving parameter. The leading aim to find the gold standard architecture it's ready to exploit the ILP (guide stage Parallelism) that exists within the benchmarks with the minimal set of resources, i.e. the ultimate silicon efficiency.

We need to find the most appropriate triplet n-manner (Nbways), guide utilization rate (Tuse) and chip enviornment. The processor frequency and the resulting Nbop/sec are derived from the design for every different n-way architecture.

As no compiler is purchasable for every evaluated architecture, the most effective technique to find the most fulfilling triplet n-approach -instruction utilization cost and chip area is to manually agenda operations in execution kernels in keeping with each and every architecture. The assembly code of the recognized hotspots has been written and the corresponding execution time (in clock cycles) in keeping with the records dependencies and the guideline utilization fees had been calculated for distinctive parallel architectures (2, three, four, 6 and 8-means architectures). They regarded two types of data-paths : homogeneous facts-paths have the same processing components whereas heterogeneous architectures have particular processing substances for every approach of the facts-course.

For their audio-speech benchmarks, on homogeneous data-paths, the guide utilization fee is 87% for a 2-approach VLIW, 74% for 3-approach, 54% for four-manner and fewer than 36% for wider architectures. without doubt, the hotspot loops of the audio applications haven't enough ILP to effectively make the most 6 or 8-method architectures. The instruction utilization expense on heterogeneous architectures is 87% for a 2-way, seventy two% for three-approach and 52% for 4-approach architectures, as shown in figure 2.

Heterogeneous facts-paths allow an important structure area keep. on the equal time, the utilization quotes of each homogeneous and heterogeneous statistics-paths are rather similar. So, coping with silicon effectivity as the main metric, the use of parallel architectures with heterogeneous processing supplies is terribly unique. they are able to only consider heterogeneous 2, 3 and 4-way architectures in the leisure of the paper.

figure 2: guide utilization rates for n-manner architectures for audio benchmarks

The second step is to opt for the quantity of parallelism within the architecture. This step wants a prediction of the evolution of the hardware complexity when duplicating elements. From a RISC processor dimension distribution, they estimate the chip enviornment of every parallel architectures based on right here speculation :

  • The decoder hardware complexity is about 5% of the typical chip enviornment.
  • The fetch charge is additionally about 5%.
  • The chip enviornment of a register file of 32 32-bit registers is about 35%.
  • The execution instruments are alleged to use 40% of the normal area.
  • The closing 15% are assumed for the final elements of the pipeline with its communique mechanisms and pipeline registers.
  • The evolution of the hardware complexity of distinctive architectural facets is also estimated. for instance, they agree with that the software memory access charge is proportional to the variety of fetched guidelines per clock cycle. When n increases with n-method architectures, the decoder complexity raises, but many operations have mutual decoding. thus, they anticipate that the decoder enviornment increases proportionally to the square root of the cost n. Bypassing and communique mechanisms are additionally assumed to raise in keeping with the equal legislation.

    as the register file and the execution contraptions characterize around three/four of the typical chip area, they made some certain investigations to estimate extra precisely their evolution when n raises. For the register file, a collection of gate degree synthesis in accordance with 2R/1W RF description has been achieved. This analyze suggests an increase of 50% when doubling the variety of RF ports, a rise of 100% with a 6R/3W RF and over 2.5 boost aspect for an 8R/4W RF versus the fashioned 2R/1W one. In table 5, they current the hardware complexity evolution of n-method processors fairly to the RISC area complexity.

    desk 5: Hardware complexity evolution for n-means architectures with heterogeneous statistics-paths especially to RISC processor

    Having evaluated each of the parameter presented in the equation three, they can consider the distinct n-way architectures versus the scalar implementation (i.e. bypassing the Nbop/sec that isn't already universal). 4 their look at case, 2 and 3-way architectures characterize a fine exchange-off for audio-speech purposes.

    2.4 building tool

    The Synopsys Processor fashion designer [8] is an automatic design device from the ADL (structure Description Language) LISA 2.0. It allows for an efficient design comments to debug and optimize the architecture. From a behavioral description of the operations, a few architectures (RISC, DSP, VLIW) can be carried out. additionally, an architecture debugger offers a complete visibility of the parameters on the execution time : registers, contents of the distinctive reminiscences, instruction opcodes, pipeline levels, stalls and flushes, loop iterations, latest pipeline indicators, etc. It permits a micro-step execution of the LISA directions, it is neither cycle-correct nor guide-correct however ”LISA-line-accurate”.

    This tool is used to measurement a design criteria and to abruptly evaluate its influence on the main gadget. The development stream and the tool features used are introduced in figure 3. From the beginning factor defined in the past, this device is used all through the guided search process described in figure 1,c) of the section 1.

    determine three: Audio Processor Design with Synopsys

    three. structure OVERVIEW

    A block diagram of the designed processor is offered in figure four.

    This figure suggests a 5 pipeline stage structure: guide Fetch (FE), Decoding (DE), Execution (EX), reminiscence or 2nd execution stage (MEM) and RF Writeback (WB). A n-approach structure with three separate records-paths. The distribution of the operators by data-route turned into acquired from the applications analysis and their computational patterns. The guide utilization cost estimated gives a top level view of the rightness of the alternative. This distribution is given under :

  • information-direction 1 : Arithmetic and good judgment Unit, Jumps and Branches, and a 16x16!32-bit Multiplier.
  • statistics-course 2 : Arithmetic Unit with CC Flags version and a Shifter.
  • information-course three : ALU, Load/save Unit, statistics Manipulation (including Conditional Writes).
  • All these data-paths are 32-bit signed except the multiplication. The multiplier takes 16-bit operands and explicits indications to be able to assist wider software (un)signed multiplications. The 16x16!32-bit multiplication is done in the MEM (or EX2) stage in an effort to no longer extend its crucial route (i.e. processor crucial path) with the data hazard resolution. The multiplier influence can be used within one cycle latency. The guideline-set coding is ninety six-bit wide with primarily two supply operands and one register result (Opcodedestreg, src1reg, src2reg−or−imm). The 2nd operand can be a register or an immediate cost mostly 14- bit extensive. The Register File comprises 32 32-bit registers. it's absolutely obtainable via the three information-paths: it includes 6 examine and 3 Write ports. The department and jump unit isn't represented during this determine. The corresponding guidance are carried out with the aid of the decoder and the result is given returned to the fetch stage. Branches and jumps are delayed by one clock cycle, which capacity that the prolong slot should be filled via a useful guide or a NOP. Like already presented within the illustration of Conditional Codes Flag Implementation, a conditional move is implemented, that either writes first or 2nd operand to a register cost according to the state of CC flags. This technique replaces conditional branches through conditional transfers. Its utilization increases performances as a result of availability of statistics-paths and liberating condition evaluation ready. the weight/shop Unit allows data memory entry. It has 4 entry modes : ”.W” to govern note-class facts, ”.H” for signed half-be aware-large information, ”.UH” for equal vast unsigned one and ”.B” for eight-bit one. All these entry are finished in the MEM stage which means one cycle latency to use the loaded outcomes.

    figure 4: architecture Overview

    4. results AND VALIDATION

    four.1 structure Design

    The designed three-way VLIW ASIP VHDL RTL has been generated the use of the Synopsys Processor fashion designer tool. RTL has subsequent be gate-degree synthesized the usage of Design Compiler from Synopsys targeting sixty five-nm Low energy TSMC technology. below a minimum time constraint of 2.8ns, the typical chip area is about 0.07mm2 with more than forty five% committed to the Register File and 13% to the decoder. The validation process consists in executing the profiled purposes and evaluating the processor performances in terms of Silicon effectivity. figure 5 summarizes the average design movement from the software benchmarks to the ASIP performance contrast.

    figure 5: Methodology Design flow

    First, they select a group of benchmarks from the application area that they profile and analyze. Then, they search for the superior triplet variety of guidance performed in parallel - guide utilization expense and chip enviornment. For this, they assess how the assembly code of the different benchmark kernels execute on each n-means architecture and they evaluate the execution time and the guide utilisation cost. Third, they use a design device to measurement an effective processor. They iterate the technique except they meet their necessities. finally, they validate the designed processor with a gate-level synthesis and they execute the studied hotspots kernels.

    As no compiler become attainable, the meeting code of three hotspots became manually-written and optimized to validate the ASIP structure. The hotspots of the profiled functions were completed on the processor resulting in an guideline utilization fee of 86%. They be aware that simplest three of the 14 hotspot capabilities have been manually-written to evaluate their processor. They best represents about 20% of the ordinary execution time. The Silicon efficiency of a processor is given by way of:

    The silicon efficiency of the designed ASIP is then:

    The designed three-means processor grants about 13GOPS/mm2. The construction lasted a couple of months. Its clock speed is set 357MHz and it executes efficiently GSM (world device for cellular communications), CELP, ADPCM (Adaptive Differential Pulse Code Modulation) and MP3 purposes.

    4.2 performance evaluation

    The Synopsys Processor clothier allows for a fast generation of other Audio ASIP versions in response to the designed one. The goal to the offered design methodology is to show that the design parameters have been appropriately sized. A small change of one of them leads to completely distinctive outcomes. In an illustration earlier than, they confirmed the have an effect on of enforcing two distinctive conditional codes flags. Now they accept as true with the influence of smaller guidelines.

    Few changes are accomplished to the ADL description to design 2-method VLIW and RISC implementations. Evaluating their performance with the audio benchmarks results in distinct results in silicon efficiency as offered in determine 6.

    figure 6: Normalized silicon efficiencies finished by way of distinct n-method processors

    For the three evaluated hotspot services, they evidently study that n-way architectures are improved than scalar ones. at the start of the analyze, taking best these three hotspots, three-way architecture changed into 0.78 times much less effective than the 2-way one in terms on Silicon efficiency. however for all the hostpots, the two types have been reasonably similar. The consequences given in the figure 6 after implementation refer handiest to the execution of the three hotspots. So if they anticipate that the evolution from the preliminary effects to the outcomes after implementation might be the identical for all the hotspot functions, then they are expecting that the 3-method processor may be 1.23 instances more desirable than the two-manner one and much more versus the scalar implementation.

    SPARC v8 is an guideline-set for RISC processors together with load/shop, arithmetic, good judgment and shift guidance and all the fundamental stuff for executing a huge amount of functions. They select the Leon3 implementation of the SPARC v8 ISA to be their referent for the ASIP efficiency performed. The Leon3 has a seven stage pipeline with a Harvard structure (with separated software and facts recollections). It includes a hardware multiplier/divider and a three-port Register File. The special register file consists of 32 registers organized in home windows. The three validation features are executed on it and its RTL implementation is gate degree synthesized with the equal Low-power TSMC library. The normal design dimension is ready 0.035mm2 with a clock pace of 357MHz. In desk 6 they compare both the results of the designed three-manner ASIP and the consequences of the Leon3 processor executing the audio applications. With the described design methodology, the audio-speech three-way ASIP is about 70% more effective than the Leon3 processor.

    table 6: Audio ASIP vs Leon3 Silicon Efficiencies

    5. CONCLUSION AND FUTURE WORK

    The applied methodology allowed a fast Design area Exploration and a good sizing of the key parameters. Their methodology has a few barriers:

  • Manually assembly coding an entire benchmark can’t be finished to select the appropriate structure sizing. within the audio illustration, they modeled over sixty six% of the set of their benchmarks. This leads us to the alternative of a three-approach architecture, however they have no warranty that the remaining 34% would now not modify this choice.
  • Predicting the evolution of complexity can infrequently be completed if they are faced to advanced gadget designs with hierarchical recollections and complex network connections.
  • The designed VLIW ASIP became very efficient in terms of efficiency. however its Silicon effectivity changed into badly reduced by means of its chip area. They observed that the Register File took over forty five% of the normal enviornment. In future works, they can center of attention on cutting back the average system silicon charge.

    REFERENCES

    [1] Karlheinz Brandenburg, Oliver Kunz, and Akihiko Sugiyama. Mpeg-4 herbal audio coding. signal Processing: picture communication, 15:423–444, 2000.

    [2] M. Budagavi and J.D. Gibson. Speech coding in cellular radio communications. proceedings of the IEEE, 86(7):1402–1412, July 1998.

    [3] Andres Vega Garcia. M´ecanismes de controle pour la transmission de l’audio sur l’cyber web. PhD thesis, satisfactory- Sophia Antipolis institution, October 1996.

    [4] A.S. Spanias. Speech coding: an educational overview. proceedings of the IEEE, eighty two(10):1541–1582, October 1994.

    [5] http://www.ibm.com/developerworks/linux/library/lgnuprof.html?ca=dgr-lnxw02gnuprofiler.

    [6] N. Pinckney, T. Barr, M. Dayringer, M. McKnett, Nan Jiang, C. Nygaard, D. cash Harris, J. Stanley, and B. Phillips. A mips r2000 implementation. pages 102– 107, June 2008.

    [7] P. Bannon and J. Keller. interior structure of alpha 21164 microprocessor. In Compcon ’95.’applied sciences for the tips Superhighway’, Digest of Papers., pages 79–87, Mar 1995.

    [8] Karl V. Rompaey, Diederik Verkest, Ivo Bolsens, and Hugo D. Man. Coware - a design environment for heterogeneous hardware/utility systems. EURO-DAC, pages 252–257, 1996.


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