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IBM v3 Practice Test

establishing a Reusable IP Platform inside a device-on-Chip Design Framework focused against an academic R&D ambiance | 000-N19 test Questions and test Questions

by using Brendan Mullane and Ciaran MacNamee,Circuits and equipment research Centre (CSRC),institution of Limerick, Limerick, eire

abstract:

A key problem dealing with the semiconductor trade is to mix intellectual Property (IP) from quite a few sources without delay and efficaciously. Design instances are at all times pressurized by means of time to market necessities and increasing complexity. Industrial practices for establishing device-on-Chip (SoC) IP have evolved below these pressures, but applying these practices in an academic atmosphere items extra challenges. The theory for constructing a framework for generating IP turned into based on this reuse revolution and the merits it brings to R&D. The skill to design excessive excellent IP and to allow work practices for reuse methodology helps to obtain working SoCs in a timely and efficient method. This paper describes a technique for implementing IP reuse practices acceptable to an academic environment.

1. Introduction

a considerable number of components are vital for productive IP use, flexibility of integration, stronger ease-of-use, minimized charge, and decent work practices for developing IP. This paper is according to specific work constructing an ASIC the use of 0.35ìm system technology. The architecture in this IC is similar to SoC designs that use an 8-bit CPU and linked peripherals. it's proven that the framework for IP building based all through this assignment can be sure a success deployment of both current and new designs in future projects.

The present vogue in SoC design is to make use of current IP as much as feasible. IP in the kind of CPUs, DSPs and controllers, are being reused in new IC projects at semiconductor methods design properties. Engineering teams now design chips with hundreds of thousands of gates in under a 12 months. just recently, such productiveness would were unattainable, even unthinkable with out hardware IP reuse. Most educational environments do not need the substances and infrastructure to permit such engineering potential, despite the fact the underlying ideas of reuse can be utilized to allow more advantageous IP era and expertise retention for positive R&D.

This paper introduces a collection of guidelines and a methodology used to ensure a constant method to designing IP and to enable for reuse of those modules in future initiatives. the first stage turned into to examine highest quality industrial practice. Work describing the ASIC construction cycle and its have an impact on on IP technology changed into performed. a collection of requisites for ensuring IP excellent and ease of integration was also prepared. A key objective become to make sure skills can be retained within the institution centre to have in mind expected graduate turnover.

2. IP Reuse Framework in CSRC

A review of the common considerations in design use and reuse turned into initiated [1]. a variety of IP standards had been reviewed and these blanketed Freescale’s Semiconductor Reuse common [2], VSI Alliance’s set of standards for developing SoCs [3] and OpenMORE [4]. IP reuse might certainly not have happened without necessities or with out the underlying infrastructure [5]. Design and verification reuse, a truth of lifestyles these days for many SoC designs, ensures the productivity hole is kept manageable[6]. Design reuse regarded a simple theory that can also be with ease adopted, has persevered to be difficult in observe. problems exist in getting engineers to believe that reusable IP will work every time it is used in an IC. presenting IP aid capabilities and adoption of a proper verification process develops this have confidence.

2.1 SoC architecture and Infrastructure

The purpose of this venture become to establish a design methodology for producing IP. The methodology involved architectural decisions and choice of design-flows for IP construction accompanied through the prerequisite IC design tools. task criteria such as the SoC architecture, third-birthday celebration core use, in-residence IP building and the system bus interface have been all considered before the IC structure became concluded and the peripheral integration became performed. The fundamental SoC architectural diagram is shown in figure 1 and the comprehensive chip was taken through verification and the returned-end tiers of synthesis, layout, static timing analysis and ultimate design rule checking.

figure 1: SoC Design structure

the following key choices have been made when it comes to the IP help constitution.

2.1.1 Peripheral Bus Interface

The preference of a standard SoC gadget bus for connecting the CPU to the equipment peripherals changed into critical to the ambitions of this challenge. using a standardized bus architecture is simple to setting up reusable IP. quite a few bus necessities have been investigated for the wants of the CSRC IC initiatives. The 8051 CPU changed into used in this design and although the inner particular characteristic Register (SFR) bus become regarded, the authors wished to employ a standard bus design to be reused in other IC implementations.

lots of the most important IC and IP agencies base their IP portfolio building around a single SoC bus structure. Semiconductor organizations such as ARM and LSI common sense use the open supply AMBATM [7] bus common. IBM uses its personal proprietary CoreConnectTM [8] bus regular. The OpenCores initiative makes use of the WishboneTM [9] described bus interface. The authors accompanied that the AMBA bus architecture was well supported amongst the IP vendor group. This huge acceptance arises from the availability of an open bus average it is license free and well proven in current SoC designs. shoppers have a high degree of confidence choosing IP this is regarded dealer independent. moreover, the AMBA bus is well supported with the aid of EDA organizations providing verification support. The AMBA bus turned into chosen because the bus interface for CSRC SoC projects for these explanations.

The AMBA bus allows partitioning for modular designs[10]. Its methodology for embedded processor design encourages both a modular and first time appropriate system design. It additionally hastens product migration with the aid of helping module reuse. In certain, the AMBA APB bus specifies a versatile interface and small overhead aid for low bandwidth peripherals. The IP design the use of the AMBA interface is made simpler through partitioning the excessive-end and low-end contraptions within the gadget and helps power efficient designs. the entire peripherals in this design used the AMBA - advanced Peripheral Bus (APB) as the standardized interface. The CPU as a single bus grasp changed into interfaced to the entire peripherals by means of an in-condominium designed AMBA bridge interface.

The advantages of the use of a common bus interface for core construction are smartly documented [1, 10, 11]. A pattern AMBA APB register module, proven in figure 2, became effective for demonstrating the favored interface design to postgraduates. The RTL code for this module helped the team to have in mind the principles of good coding follow to encompass parameterization and validated using revision manage for code alterations and worm fixes. the entire IP developed in this IC challenge can be reused in another AMBA based SoC applications and this aids future product and platform construction

figure 2: pattern APB module

2.1.2 3rd party Core Licensing

a further enormous task become to designate an appropriate microcontroller for the mission. The IP community became approached with reference to licensing of the CPU and debug cores. there were a few facets to licensing IP cores from an educational standpoint. It changed into simple to make certain a licensing arrangement turned into made the use of a non-business analysis- licensing mannequin. Many providers were most effective prepared to license their cores in response to a full business association and the prices quoted have been beyond an tutorial analysis finances. Some providers were willing to agree with a reduced non-commercial license payment with the re-introduction of full costs provided the IC proceeds to industrial utility. different IP vendors restricted their set of deliverables to FPGA netlist implementation handiest. This confined their choice of third birthday party CPU and debug cores. fortunately, some IP businesses had adventure coping with academic situations and have been prepared to release IP deliverables and help for non-business analysis pastime at a decreased cost. The main creator changed into in a position to perform a survey of suitable cores and got here to an contract for the third party IP obligatory for the SoC assignment.

2.1.three Design Flows

The ASIC design movement and electronic Design Automation (EDA) tool alternative is an important element of an effective IP framework. The option of equipment must complement the design flows and support reusability of IP. The centre accesses device units provided as educational programmes from the semiconductor EDA groups. The CSRC also has access to regular EDA tools by way of the Europractice[12] software provider scheme. Their FPGA and Digital design flows were drawn up across the availability of these tools and to devise the SoC IP development and integration. These flows were effective in deciding on the diverse degrees involved in the development of IP and SoC designs. in addition to the digital design move, a move for FPGA prototyping became also added. The FPGA development enables for an affordable design validation platform and adds self assurance by means of making certain suitable behavior earlier than final tape-out.

2.1.three.1 Digital IC Design stream

The digital design follows the basic ASIC implementation route. a few semiconductor business web sites and technical paper searches printed the general design circulate that exists for digital ASIC design [13], [14].

figure 3: Digital IC design stream

The design stream and equipment alternative as drawn up in figure three had been adapted to device availability and the alternative of IC procedures supplied by Europractice.

2.1.three.2 FPGA Design movement

The FPGA stream in figure four is very similar to the digital IC design flow, but the design tools to implement and application a FPGA design are diverse. The project used the Xilinx design kits and tools made obtainable by the use of the Xilinx tuition Programme. They used Xilinx Spartan 2 and 3 boards to put in force the digital design features. The Xilinx ISE webpack is a set of equipment that takes Verilog RTL code and runs it through synthesis, physical layout to gadget configuration. The ultimate bit file can then be downloaded to software the FPGA device to examine the purposeful behavior of the digital design. FPGA verification suggestions and their significance in design validation and reuse are mentioned later.

figure four: FPGA Design move

2.2 CAD Infrastructure

The CAD infrastructure turned into enhanced to carry out SoC building inside the centre. The fashioned constitution included three low-grade UNIX servers for operating the IC design tools and holding challenge records. A plan changed into initiated to upgrade the IT hardware wants. every of the person PCs were installed with VMware Linux, permitting users to keep their home windows OS however greater importantly every computing device might use its own CPU processing vigor with Linux to deliver greater performance. Two high vigor Linux mainframes, received for preserving the venture databases were also utilized as license servers for the supported EDA equipment. the brand new set-up gives the performance requirements to perform IC R&D in the CSRC centre.

an extra step became picking the EDA tools integral for IP development. equipment for verification and making certain nice of RTL code had been now not in vicinity. youngsters using their Europractice membership, the centre had entry to popular EDA tools at a reduced charge. tools such as ModelSim for RTL verification and Leda for RTL evaluation were received. The existing edition of Design Compiler turned into additionally upgraded according to trade requirements.

3. Design Methodology and IP reuse Implementation

utility of reuse will pay off when it comes to construction charge and time-to-market. This section summarizes the development milestones for a standard IP design. Defining the stream and associated design stories helps assure a repeatable, high great, and reusable block of peripheral IP. an extra improvement of a documented stream is that other design organizations can use this system to strengthen IP in a similar method; making certain IP is constant in its implementation, integration move, deliverables, and usual fine.

3.1 development Milestones

IP/SoC design milestones are critical to the delivery of working silicon and attaining a ‘appropriate first time’ policy. These milestones are markers positioned down throughout the development section to manipulate and measure the design pastime and progress. These markers indicate experiences occurring right through the critical stages of the design section from birth to end. Milestones take location on the herbal progression of the task. figure 5 and desk 1 describe the signal-off milestones to consist of all main design reports.

determine 5: IP construction Milestones

desk 1: IP building degrees

stageReview Description FSR purposeful Spec overview purposeful specification is finished, particulars on effort estimation, work breakdown structure and schedule. DSR Design delivery assessment Design birth, working towards, RTL coding & synthesis guidelinesTPR check Plan evaluation finished specification of verification atmosphere, look at various circumstances, bus-fashions, transactors. RCR RTL Code assessment RTL bug fixes recognized via exhaustive verification & RTL Lint/code checking TLR Trial design evaluation establish floorplan and operate P&R. Floorplan in accordance with module connectivity, unravel congestion and timing –look at clocking FVR ultimate Verification evaluate excessive priority trying out achieved. commonplace bugs in the RTL are fastened. coverage analyzed. Low precedence trying out ok. FDR closing Design overview review integrity exams (DRC, LVS) STA, verify Vectors and remaining gate-level verification with finished design timing.

three.2 venture Database constitution

A standardized directory constitution is a must-have for IP reusability. an efficient and simple to use database constitution ensures compatibility and consistency of peripheral design. IP construction includes specification, coding and verification as key design tiers. because of this, many help file codecs are required. IP renovation is additionally a key theory in IP reuse. The capability to log and keep music of design adjustments is a must-have to the ordinary great of the design. determine 6 shows the CSRC directory structure to help the IP development stages.

figure 6: normal CSRC listing Database

3.3. Reuse instructions

3.three.1 Specification reports

The design studies are giant in terms of generating a framework for IP building and reuse. These reports aid documentation and confirm first rate design practices.

three.three.2 functional Specification

This document gives an in depth useful description of the module and is written prior to the IP construction. The FSR assessment takes place to be certain all features of the peripheral functionality are lined. The specification can be used to start the design and RTL coding. The practical specification needs to be up to date as a consequence with any additional points requirements. The CSRC uses a draft template document as a guideline for producing practical block and IC design requisites.

three.3.3 RTL Coding and analysis

RTL building contains coding the peripheral in a hardware description language such as Verilog or VHDL. Verilog RTL turned into used and a collection of coding instructions for the IP generation was issued. This set of coding ideas ensures consistency, coding vogue high-quality and provides for more suitable maintenance. The RCR is a high stage evaluation of the RTL code to make certain it is stylistically appropriate and maintainable. The intent is to double-examine the code nice. The foundation for this evaluate is the RCR guidelines. RTL analysis is carried out the usage of Leda for crosschecking RTL code suggestions against the Reuse Methodology guide (RMM). preliminary FPGA/IC synthesis can even be used to highlight any RTL concerns with reference to synthesis.

three.three.4 Revision control

Revision control is vital to the idea of design reuse and ensures vital tips is not misplaced during the design section. Revision manage and file administration is exceptionally essential all over RTL coding as any code lost all the way through this stage can critically affect the average design timeline. To help control data, engineers use source manage management systems. These are typically bundled with the Linux working programs or obtainable from GNU (RCS, CVS, Subversion). These code management methods provide a complete background of each file as separate models.

three.three.5 trojan horse renovation

coping with bugs is an important consideration for any design framework. it's standard to find practical irregularities within the design and their incidence doesn't reflect the capabilities of hardware designers. once a problem is recognized, it must be resolved. All design groups want a way for tracking issues and making certain their decision. The authors proposed preserving a worm record for any design related concerns.

3.4 Verification and Validation atmosphere

The verification section is important to offering first time working silicon. Their verification methodology uses a twin track method. Verification happens on the module degree and also on the SoC system degree. The Module Verification ambiance (MVE) functionally validates the core and ensures all design features have been comprehensively established. The SoC Verification ambiance (SVE) assessments the cores’ conduct on the system stage and in particular exams the connectivity between the core interfaces. An FPGA/ASIC design verification strategy was used to validate the mission at the equipment SoC level.

three.four.1 Module Verification environment (MVE)

an essential part of the MVE was the era of the APB Bus useful model (BFM) to generate the functional conduct of the gadget bus. all the peripherals have been based on this standardized bus structure and this enabled the use of a familiar mannequin to look at various the bus interface and registers contained within the peripherals. This model additional offered a simple to make use of check ambiance. The diagram in determine 7 illustrates this. The BFM utilized Verilog projects for read/write accesses, together with wait state manage and become reused in all the peripheral check environments. The BFM become positive for operating assessments to obtain self assurance in the purposeful habits and for targeting high code insurance.

determine 7: APB Bus functional model

3.four.2 SoC Verification environment (SVE)

The SVE consisted of a separate however similar look at various solution for FPGA prototyping and the ASIC device degree verification. The FPGA solution became helpful for mapping the comprehensive SoC RTL code to encompass the CPU, debugger and the entire peripherals onto a FPGA. determine eight illustrates the fundamental structure carried out onto the FPGA device.

figure eight: FPGA Prototype Validation

The CPU and other main peripherals are linked collectively as a single platform and assessments have been developed in R8051 CPU core program code to function the peripheral assessments. The ASIC verification atmosphere is corresponding to the FPGA test bed, except during this case all assessments have been run using RTL and process specific gate-level stimulations. each and every of the peripheral firmware exams developed for the FPGA prototyping were reused at ASIC gadget level.

4. results and Conclusions

The venture goal turned into to put into effect a SoC design framework for the delivery of reusable IP. The selected usual system bus aided the building of plug and play peripherals that may also be reused in many other SoC applications. The building of the 8051 CPU external facts bus to equipment bus-bridge provided for a standardized interface and simplified the peripheral construction.

The design flows of Figures 4 and 5 were followed to make certain a constant design method for the construction and equal aid for trade ordinary EDA equipment. The directory structure as defined in area three.2 was additionally critical for associating data with each and every stage of the IC development and protecting a smartly-managed database. every of the carried out IP blocks follows this well-known database constitution and this ensures reusability going forward. Design reports ensured self assurance and nice of the IP block design. The Verilog code become reviewed to be sure revision control and RTL coding instructions have been adhered to. an identical evaluation became conducted to ensure the verification environments at module and device level had been applicable to verify the functionality of these designs. The RTL changed into validated on a FPGA equipment and exams have been conducted at the device level to verify the peripherals related to the 8051 CPU.

The IP framework as mentioned during this paper is proper for implementation in an tutorial centre wishing to carry out a reusable IP programme. this methodology and reuse suggestions are universal in business, but due to funding and useful resource constraints, can also not always be handy to deploy in an tutorial environment. This paper discusses the implementation of IP development for reduce bandwidth peripherals; in spite of this the underlying concepts of IP use and reuse are the identical.

four.1 tutorial Centre Specifics

staff requirements for analysis are in the end resourced from graduates pursing MEng and PhD levels. within the CSRC, staff and tutorial researchers are answerable for main tasks and mentoring students. The graduates need abilities development to carry them as much as velocity and having a structured construction methodology enables deliverables to be met in a well timed trend. The advantages of IP advantage retention changed into another reason for introducing the IP building framework, as work generated on projects conducted in the past would had been complicated to growth once postgraduates had accomplished their research degrees. This was a vital challenge to resolve, as beneficial undertaking work conducted during the past may additionally were unnecessarily misplaced.

four.2. Future recommendations

The cores can be additional stronger via providing a equipment C or C mannequin as part of the developmental tiers to additional the degree of abstraction and to pace up design verification and software building.

SystemVerilog is a hardware design and verification language with advanced facets supposed to support users increase reusable, transaction-level, coverage-pushed testbenches. strategies reminiscent of statement based mostly Verification (ABV) can be applied to the bus protocol to computer screen pin recreation and the utility of insurance-pushed exams add confidence in working silicon and provide an exhaustive testing atmosphere. These points introduce ideas of verification reuse.

Design for verify (DfT) is commonly excluded from the design circulate in an academic atmosphere. DfT is a very important characteristic crucial for IP reuse. The IEEE 1500 general for Embedded Core look at various (SECT) specifies a core wrapper design to accommodate DfT elements. This IEEE 1500 compliant wrapper design could provide a helpful extension to the present IP building tiers.

5. Acknowledgements

The authors well known the assist of the Circuits and programs analysis Centre (CSRC) in the electronic and desktop Engineering (ECE) Dept. on the institution of Limerick.

6. References

[1] Australian Microelectronics network, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse commonplace v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA architecture doc v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "making use of the OpenMORE evaluation application for IP Cores," in ISQED 2000: Synopsys, Mentor snap shots, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded application reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - functional Verificaton of HDL models", Kluwer academic Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, can also 1999.

[8] IBM. CoreConnect Bus. structure, "http://www-03.ibm.com/chips/items/coreconnect/."

[9] R. Herveille, "WISHBONE equipment-on-Chip (SoC) Interconnection architecture for portable IP Cores," OpenCores firm, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "flexible, requirements-primarily based IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore good judgment, "QualCore SoC stream."

[14] V. P. Nelson, "VLSI/FPGA Design and look at various CAD device circulate in Mentor photos," Feb 15, 2006.


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