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It’s time to cast your vote for the 2018 DesignCon Engineer of the 12 months. This award is given out each 12 months all over DesignCon and seeks to appreciate the best of the top of the line in engineering and new product advancements at the chip, board, or system level, with a different emphasis on signal integrity and vigor integrity.
The editors of Design information and the personnel of DesignCon would want to present hearty congratulations to the nominees. For this 12 months’s award, the winner (or his/her representative) may be able to direct a $10,000 donation to any secondary educational establishment within the united states. The particulars on every nominee are below as offered in their published biographies and through the adult/s who made the nomination. solid your vote right here.
vote casting closes at noon eastern Time on Friday, January 12, 2018. The winner could be introduced at DesignCon 2018, January 30-February 1, at the Santa Clara convention middle, Santa Clara, CA.
The six finalists for the 2018 DesignCon Engineer of the 12 months Award are (click on each name to see finalist’s bio and neighborhood exercise):
Mike Peng Li
Dr. Mike Peng Li is a Fellow at the Programmable solution neighborhood (formerly Altera Corp.), Intel supplier. he's a company skilled and adviser on jitter, noise, signal integrity, high-speed link, SERDES and on-die instrumentation (ODI), electrical and optical signaling, silicon photonics, and optical FPGA. Dr. Li become the chief expertise Officer (CTO) for Wavecrest enterprise from 2000-2007, where he led the technology roadmap, leadership, imaginative and prescient, and product traits.
Mike has been a robust suggest for verify & measurement, and sign integrity subject matters in the DesignCon community for greater than 15 years. He has worked on many technical papers and panel courses related to the subject area of jitter & noise on serial information signaling. Mike has proven management within the industry on constructing interest and figuring out round jitter courses for essentially 2 a long time.
Mike has served on the DesignCon Technical software Committee for over 15 years and leads convention planning as a co-chairperson for track 9, covering measurement, simulation, and optimization of jitter, noise, and timing to minimize errors. he's a standing member of the "Case of the Closing Eye" panel held annually at DesignCon and is an IEEE Fellow and chair/editor/member of OIF, IEEE 802.three (Ethernet), PCI-SIG, and HMC standard committees.
This year at DesignCon, he is providing on the tutorial, “Design & Verification for top-velocity I/Os at 10 to 112 Gbps With Jitter, signal Integrity, and energy Optimization,” the panel, "The Case of the Closing Eyes: Is PAM the reply?" and presenting within the technical classes “Behavioral FEC models for high pace Serial hyperlink BER Simulation,” “effective hyperlink Equalizations the usage of FIR, CTLE, FFE, DFE, and FEC for Serial links at 112 Gbps and beyond,” and “Signaling and efficiency Challenges and options for next-generation OIF CEI-112G-VSR "Chip-to-Module" Interfaces.”
cast your vote for the 2018 Engineer of the 12 months by noon ET, January 12.
Senior staff Engineer, Advantest
Jose Moreira is a senior workforce engineer within the check mobilephone innovations team of the SOC business unit at Advantest in Böblingen, Germany. Mr. Moreira existing work is on the challenges of IC characterization and trying out, specially check fixture design for high-velocity digital, mmwave (5G) and silicon photonics. He joined Agilent applied sciences in 2001 (later Verigy and in 2011 bought by way of Advantest) and holds a master of Science diploma in Electrical and laptop Engineering from the Instituto advanced Técnico, Lisbon university, Portugal. he's a senior member of the IEEE and co-creator of the book An Engineer's e-book to automatic trying out of high-speed Digital Interfaces.
Jose has been a driving drive behind IEEE P370 which advances the know-how at the back of de-embedded S-parameter measurements. He leads with the aid of instance and robotically offers simulations, measurements and shows of very excessive high-quality and conveys the material in an easy to comply with format.
This yr, Jose will be collaborating in the DesignCon panel, “Working toward 5G: What's New From outdated Generations,” and proposing in the technical session, “A NIST Traceable PCB package for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics.” Jose is an energetic member of the Technical software Committee and serves as a co-chairperson heading in the right direction 3, photonic and electronic signaling, and has been a member of IEEE P370 for the previous 2 years.
solid your vote for the 2018 Engineer of the 12 months by using midday ET, January 12.
Senior major Engineer, Oracle
Istvan Novak is a Senior precept Engineer at Oracle. anyway signal integrity design of high-velocity serial and parallel buses, he is engaged in the design and characterization of vigour-distribution networks and applications for mid-range servers. He creates simulation models, and develops size options for energy distribution. Istvan has 20 plus years of experience with high-pace digital, RF, and analog circuit and gadget design. he is a Fellow of IEEE for his contributions to signal-integrity and RF size and simulation methodologies.
Istvan’s decades of huge contribution toward the advancing of sign and vigour integrity capabilities and practices have earned him a popularity of respect and admiration among his peers. His contribution to power and signal integrity evaluation and measurements has made it viable determine and dispose of issues before they take place. His work through suppliers and academia has influenced and pushed a transformation within the techniques design, analysis, and measurement is performed during the trade.
Istvan has been presenting and instructing engineers at DesignCon for decades. he is considered an business knowledgeable on vigour integrity and his papers proceed to get reviewed and referenced 12 months after 12 months. he's with ease approachable, chuffed to support younger engineers. This year, Istvan might be collaborating in Tuesday’s keynote panel, “SI/PI & EMI Challenges: looking ahead through 2023,” and the panel discussion, “Temperature and Bias elegant Passive component models.” he'll even be offering in technical classes, “How Spatial adaptation of Voltage Regulator Output Impedance depends on feel factor and bypass Capacitor places,” “Measuring existing and present Sharing of DC-DC Converters,” and “tale of a Differential Pair size.” Istvan is an lively member of the DesignCon Technical program Committee, sharing his capabilities via participating in the evaluate of content for distinctive tracks.
Istvan is an IEEE Fellow and has been a tutor on the school of Oxford, Oxford, UK for the previous 10 years. He has also been a college member at CEI Europe AB when you consider that 1991 and served as Vice Dean of school, affiliate Professor at the Technical school of Budapest.
solid your vote for the 2018 Engineer of the 12 months by using noon ET, January 12.
Platform Architect, sign/energy Integrity, Intel
Vishram Pandit has been working in energy Integrity, signal Integrity and EMC container for more than 20 years of which ~14 years have been at Intel. He has been a key contributor to methodologies in on-chip vigor integrity, gadget stage energy integrity have an impact on and signal/power integrity co-design, and efficaciously deploying those on a lot of Intel items. Vishram led the vigor delivery & Integrity for reminiscence technology at Intel California from 2004 to 2008. He based SoC and DRAM gadget PDN solution house and chip, equipment and PCB vigour Integrity necessities and turned into global power start Lead at SoC building group from 2008 to 2011. As a part of the IP team, he worked with all world IPs unfold across quite a few geos and proliferated IP-SoC-Platform energy Integrity methodology. he is at present a Platform Architect discovering methods to Improve and co-optimize system vigor delivery spanning throughout PCB, package and Chip. he's evaluating platform PDN architecture, vigor rail merging, vigour management influence, IP/SoC PDN spec definition, decoupling method, and signal integrity affect on a future mobility product.
basic right through his time at Intel, Vishram led or provided technical advice on developing various new PI/SI methodologies that helped in spec building, optimization, enviornment discount rates, Platform BOM charge discount and product great development. He had huge affect on distinct business devices final analysis and certainly to the SI/PI group.
Vishram is an energetic member of the Technical application Committee and serves as a co-chair for music eleven, protecting vigor integrity in vigor distribution networks. This year at DesignCon, he is co-authored of the paper for the technical session, “Novel Isolation Scheme for Mitigating PDN Coupling.”
Vishram has acquired many awards in his container, including Divisional recognition Award for his work on subsequent era memory technology enabling and specification (energy Integrity), Divisional recognition Award for his contributions to noise mitigation for PDN in subsequent generation single-ended multi GHz I/O interfaces, Divisional focus Award for setting up on-chip PDN methodologies that saved charge be putting off the pessimism margin in the design, and Divisional awareness Award for co-optimizing across IP/SoC/Pkg/PCB to obtain charge discount and energy integrity for next technology differential velocity I/O interface. he's an IEEE Senior Member, a Member of IEEE CPMT Technical Committee on Electrical Design, Modeling and Simulation (from 2008), and listed in Marquis Who’s Who in the us: 2011-17.
His publications include authoring/co-authoring 10 online publications in Intel’s prestigious DTTC convention. Vishram is a co-author of the publication, vigor Integrity for I/O Interfaces: With sign integrity-power integrity co-design become published by way of Prentice corridor in October 2010. He additionally changed into a co-writer of a paper which acquired DTTC’s superior paper award and authored/co-authored 10 publications at Intel’s Joint Seminar on signal and energy Integrity (JSSPI). He has authored/co-authored 18 publications in DesignCon, including three most fulfilling paper awards and 3 finalists.
solid your vote for the 2018 Engineer of the 12 months by means of noon ET, January 12.
Founder and CEO, Picotest
Steve Sandler has been concerned with vigor equipment engineering for virtually 40 years. Steve is the founder of PICOTEST.com, an organization focusing on energy integrity solutions including measurement items, capabilities and working towards. He often lectures and leads workshops internationally on the subject matters of energy, PDN, and allotted methods, and is a Keysight licensed knowledgeable for EDA software. Steve Sandler often writes articles and books concerning energy supply and PDN efficiency and his latest booklet, power Integrity: Measuring, Optimizing and Troubleshooting vigour-connected Parameters in Electronics techniques become posted through McGraw-Hill in 2014. He' become the recipient of the ACE 2015 Jim Williams Contributor of the yr Award for his dazzling and carrying on with contributions to the engineering trade and talents sharing. Steve is additionally the founder of AEi programs, a smartly-based leader in worst case circuit evaluation and troubleshooting of satellite tv for pc and different excessive reliability programs.
With endless publications, consulting work and seminars worldwide, Steve has selflessly shared his analysis findings and capabilities. A nominator calls Steve a role model and truly an Engineer's Engineer.
Steve is the organizer, moderator, and surely will even be an active dialogue participant in their Tuesday keynote panel, “SI/PI & EMI Challenges: searching forward through 2023.” He will be running the technical session, “40 GHz PCB Interconnect Validation: Expectations vs reality” and the sponsored session, “Measuring and deciphering Impedance for power Integrity.” Steve will also be collaborating within the technical session, “energy Integrity for 32 Gb/s SERDES Transceivers.”
Steve is an lively member of the DesignCon Technical software Committee and reports abstracts and papers for tracks 4 (device co-design), 11 (vigour integrity), and 13 (check & dimension).
forged your vote for the 2018 Engineer of the year through midday ET, January 12.
President and Founder, Simberian Inc.
Yuriy Shlepnev is President and founder of Simberian Inc., where he develops Simbeor electromagnetic signal integrity application. He acquired M.S. diploma in radio engineering from Novosibirsk State Technical tuition in 1983, and the Ph.D. degree in computational electromagnetics from Siberian State university of Telecommunications and Informatics. He become important developer of electromagnetic simulator for Eagleware employer and main developer of electromagnetic application for simulation of sign and energy distribution networks at Mentor portraits. The effects of his research are published in dissimilar papers and convention court cases.
Yuriy conceived and delivered to market a state of the paintings electromagnetic container solver device suite and is considered an authority in his box and often posts instructing movies.
Yuriy is lively in the Technical software Committee for DesignCon and serves at a co-chair for track 14, modeling and analysis of interconnects. At DesignCon this 12 months he can be operating the technical session, “forty GHz PCB Interconnect Validation: Expectations vs reality” and the sponsored Session, “Measuring and deciphering Impedance for power Integrity.”
forged your vote for the 2018 Engineer of the 12 months by way of noon ET, January 12.
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