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IBM v1 test
by means of Brendan Mullane and Ciaran MacNamee,Circuits and gadget analysis Centre (CSRC),institution of Limerick, Limerick, ireland
A key challenge facing the semiconductor business is to mix intellectual Property (IP) from a variety of sources right away and successfully. Design times are normally pressurized by using time to market requirements and extending complexity. Industrial practices for constructing system-on-Chip (SoC) IP have developed beneath these pressures, but applying these practices in an tutorial ambiance items additional challenges. The thought for developing a framework for producing IP was in keeping with this reuse revolution and the benefits it brings to R&D. The capability to design excessive pleasant IP and to enable work practices for reuse methodology helps to obtain working SoCs in a well timed and effective manner. This paper describes a strategy for imposing IP reuse practices perfect to an educational ambiance.
a considerable number of factors are necessary for efficient IP use, flexibility of integration, superior ease-of-use, minimized cost, and respectable work practices for developing IP. This paper is in accordance with exact work constructing an ASIC using 0.35ìm technique expertise. The architecture in this IC is comparable to SoC designs that use an 8-bit CPU and associated peripherals. it is shown that the framework for IP building based all the way through this project can be sure a hit deployment of each latest and new designs in future initiatives.
The present vogue in SoC design is to utilize existing IP as a good deal as viable. IP within the variety of CPUs, DSPs and controllers, are being reused in new IC tasks at semiconductor programs design homes. Engineering teams now design chips with thousands and thousands of gates in less than a 12 months. only recently, such productiveness would have been unattainable, even unthinkable without hardware IP reuse. Most educational environments won't have the resources and infrastructure to permit such engineering ability, besides the fact that children the underlying concepts of reuse will also be utilized to enable extra constructive IP technology and skills retention for valuable R&D.
This paper introduces a group of instructions and a strategy used to make certain a consistent method to designing IP and to enable for reuse of those modules in future tasks. the primary stage became to examine optimum industrial practice. Work describing the ASIC development cycle and its influence on IP technology was performed. a set of requisites for making certain IP first-class and ease of integration become also prepared. A key aim become to ensure abilities could be retained within the school centre to take into account anticipated graduate turnover.
2. IP Reuse Framework in CSRC
A evaluate of the typical concerns in design use and reuse became initiated . quite a lot of IP standards were reviewed and these included Freescale’s Semiconductor Reuse common , VSI Alliance’s set of requirements for constructing SoCs  and OpenMORE . IP reuse might certainly not have took place without specifications or with out the underlying infrastructure . Design and verification reuse, a fact of lifestyles these days for most SoC designs, ensures the productivity gap is stored manageable. Design reuse regarded an easy theory that can also be with no trouble adopted, has persisted to be difficult in observe. problems exist in getting engineers to believe that reusable IP will work anytime it's used in an IC. offering IP aid services and adoption of a correct verification system develops this believe.
2.1 SoC architecture and Infrastructure
The intention of this task became to establish a design methodology for producing IP. The methodology involved architectural selections and selection of design-flows for IP development accompanied by means of the prerequisite IC design equipment. project standards such as the SoC architecture, third-birthday celebration core use, in-house IP building and the system bus interface had been all regarded earlier than the IC architecture turned into concluded and the peripheral integration was conducted. The simple SoC architectural diagram is proven in determine 1 and the complete chip changed into taken via verification and the returned-conclusion levels of synthesis, layout, static timing evaluation and closing design rule checking.
determine 1: SoC Design structure
the following key selections have been made relating to the IP support structure.
2.1.1 Peripheral Bus Interface
The selection of a typical SoC device bus for connecting the CPU to the equipment peripherals become crucial to the pursuits of this mission. the use of a standardized bus structure is simple to setting up reusable IP. numerous bus requirements have been investigated for the wants of the CSRC IC initiatives. The 8051 CPU turned into used in this design and youngsters the internal particular feature Register (SFR) bus changed into regarded, the authors wished to employ a common bus design to be reused in different IC implementations.
many of the predominant IC and IP agencies base their IP portfolio development around a single SoC bus architecture. Semiconductor businesses equivalent to ARM and LSI good judgment use the open source AMBATM  bus standard. IBM uses its own proprietary CoreConnectTM  bus usual. The OpenCores initiative uses the WishboneTM  described bus interface. The authors accompanied that the AMBA bus structure turned into smartly supported amongst the IP supplier group. This huge acceptance arises from the supply of an open bus commonplace it's license free and well confirmed in current SoC designs. shoppers have a excessive degree of self belief determining IP it really is regarded dealer independent. additionally, the AMBA bus is neatly supported via EDA agencies providing verification support. The AMBA bus became chosen because the bus interface for CSRC SoC initiatives for these causes.
The AMBA bus makes it possible for partitioning for modular designs. Its methodology for embedded processor design encourages each a modular and first time appropriate gadget design. It additionally speeds up product migration through supporting module reuse. In selected, the AMBA APB bus specifies a flexible interface and small overhead aid for low bandwidth peripherals. The IP design using the AMBA interface is made less difficult with the aid of partitioning the high-conclusion and low-conclusion contraptions within the device and supports power productive designs. all the peripherals in this design used the AMBA - advanced Peripheral Bus (APB) because the standardized interface. The CPU as a single bus grasp turned into interfaced to all the peripherals by means of an in-condominium designed AMBA bridge interface.
The advantages of the use of a common bus interface for core development are smartly documented [1, 10, 11]. A trial
AMBA APB register module, shown in figure 2, was useful for demonstrating the favored interface design to postgraduates. The RTL code for this module helped the group to bear in mind the ideas of good coding apply to include parameterization and established using revision manage for code adjustments and worm fixes. all the IP developed in this IC undertaking can also be reused in any other AMBA primarily based SoC purposes and this aids future product and platform construction
determine 2: pattern APB module
2.1.2 3rd celebration Core Licensing
a different giant project turned into to designate an appropriate microcontroller for the venture. The IP community became approached in regards to licensing of the CPU and debug cores. there were a few elements to licensing IP cores from an academic point of view. It turned into elementary to ensure a licensing association changed into made the use of a non-business research- licensing mannequin. Many carriers had been most effective organized to license their cores in response to a full business arrangement and the expenses quoted were beyond an educational research funds. Some vendors had been inclined to believe a reduced non-business license fee with the re-introduction of full charges offered the IC proceeds to business software. different IP vendors restricted their set of deliverables to FPGA netlist implementation simplest. This restricted their option of 3rd birthday party CPU and debug cores. fortunately, some IP organizations had experience coping with educational cases and had been organized to free up IP deliverables and guide for non-commercial analysis activity at a reduced can charge. The main author changed into able to carry out a survey of appropriate cores and got here to an settlement for the third celebration IP obligatory for the SoC assignment.
2.1.three Design Flows
The ASIC design circulation and digital Design Automation (EDA) tool option is an important element of an efficient IP framework. The option of equipment have to complement the design flows and aid reusability of IP. The centre accesses device sets offered as academic programmes from the semiconductor EDA organizations. The CSRC additionally has entry to favourite EDA tools by way of the Europractice utility provider scheme. Their FPGA and Digital design flows were drawn up around the availability of these tools and to devise the SoC IP building and integration. These flows were constructive in choosing the different ranges involved within the building of IP and SoC designs. apart from the digital design movement, a move for FPGA prototyping turned into also introduced. The FPGA construction makes it possible for for a reasonable design validation platform and provides self assurance by ensuring suitable conduct before remaining tape-out.
2.1.three.1 Digital IC Design move
The digital design follows the classic ASIC implementation route. a number of semiconductor enterprise web sites and technical paper searches published the common design stream that exists for digital ASIC design , .
figure three: Digital IC design circulate
The design flow and equipment preference as drawn up in determine three were adapted to tool availability and the option of IC methods supplied by using Europractice.
188.8.131.52 FPGA Design move
The FPGA circulate in determine 4 is terribly similar to the digital IC design flow, however the design tools to enforce and software a FPGA design are different. The task used the Xilinx design kits and equipment made accessible by the use of the Xilinx college Programme. They used Xilinx Spartan 2 and three boards to put in force the digital design aspects. The Xilinx ISE webpack is a collection of equipment that takes Verilog RTL code and runs it via synthesis, real design to equipment configuration. The ultimate bit file can then be downloaded to application the FPGA device to investigate the useful habits of the digital design. FPGA verification suggestions and their magnitude in design validation and reuse are mentioned later.
figure four: FPGA Design circulate
2.2 CAD Infrastructure
The CAD infrastructure was enhanced to perform SoC development inside the centre. The long-established constitution blanketed 3 low-grade UNIX servers for working the IC design equipment and preserving assignment records. A plan became initiated to Excellerate the IT hardware needs. each of the user PCs were installed with VMware Linux, permitting users to keep their windows OS however extra importantly each and every laptop may use its personal CPU processing vigor with Linux to deliver more advantageous performance. Two high vigour Linux mainframes, received for conserving the undertaking databases have been additionally utilized as license servers for the supported EDA equipment. the brand new set-up offers the performance requirements to carry out IC R&D inside the CSRC centre.
another step became identifying the EDA tools crucial for IP building. equipment for verification and ensuring first-rate of RTL code had been not in place. although the usage of their Europractice membership, the centre had entry to primary EDA equipment at a decreased can charge. equipment such as ModelSim for RTL verification and Leda for RTL evaluation have been obtained. The newest edition of Design Compiler turned into also upgraded in response to industry requirements.
3. Design Methodology and IP reuse Implementation
software of reuse can pay off in terms of construction charge and time-to-market. This part summarizes the construction milestones for a regular IP design. Defining the circulation and linked design reviews helps assure a repeatable, excessive best, and reusable block of peripheral IP. a further advantage of a documented circulation is that different design agencies can use this system to advance IP in an identical manner; making certain IP is constant in its implementation, integration flow, deliverables, and general nice.
three.1 construction Milestones
IP/SoC design milestones are crucial to the birth of working silicon and achieving a ‘right first time’ policy. These milestones are markers placed down right through the building phase to manipulate and measure the design endeavor and growth. These markers point out stories occurring all the way through the essential stages of the design section from start to end. Milestones take location on the herbal development of the project. determine 5 and table 1 describe the sign-off milestones to include all main design reports.
determine 5: IP building Milestones
table 1: IP development stages
useful Spec evaluate
purposeful specification is finished, particulars on effort estimation, work breakdown constitution and agenda.
Design start overview
Design start, practising, RTL coding & synthesis checklistTPR
test Plan evaluation
complete specification of verification atmosphere, look at various instances, bus-fashions, transactors.
RTL Code evaluate
RTL computer virus fixes identified through exhaustive verification & RTL Lint/code checking
Trial layout evaluation
establish floorplan and operate P&R. Floorplan based on module connectivity, get to the bottom of congestion and timing –analyze clocking
closing Verification overview
high priority checking out achieved. time-honored bugs within the RTL are fixed. coverage analyzed. Low priority checking out adequate.
ultimate Design review
overview integrity assessments (DRC, LVS) STA, check Vectors and last gate-stage verification with finished design timing.
3.2 assignment Database constitution
A standardized directory constitution is essential for IP reusability. an efficient and simple to use database constitution ensures compatibility and consistency of peripheral design. IP development involves specification, coding and verification as key design tiers. due to this fact, many guide file codecs are required. IP upkeep is also a key theory in IP reuse. The means to log and keep music of design changes is essential to the basic satisfactory of the design. figure 6 suggests the CSRC directory structure to guide the IP development levels.
figure 6: normal CSRC directory Database
3.three. Reuse instructions
three.three.1 Specification studies
The design studies are huge in terms of generating a framework for IP construction and reuse. These experiences support documentation and make sure good design practices.
three.3.2 purposeful Specification
This doc provides a detailed useful description of the module and is written just before the IP construction. The FSR review takes place to make sure all elements of the peripheral performance are lined. The specification may be used to beginning the design and RTL coding. The purposeful specification must be updated accordingly with any additional elements requirements. The CSRC uses a draft template document as a guideline for producing purposeful block and IC design necessities.
three.3.three RTL Coding and evaluation
RTL building contains coding the peripheral in a hardware description language reminiscent of Verilog or VHDL. Verilog RTL was used and a set of coding instructions for the IP era become issued. This set of coding concepts ensures consistency, coding fashion quality and provides for greater maintenance. The RCR is a high stage evaluate of the RTL code to make sure it is stylistically appropriate and maintainable. The intent is to double-verify the code great. The basis for this evaluate is the RCR checklist. RTL analysis is performed the use of Leda for crosschecking RTL code rules towards the Reuse Methodology manual (RMM). initial FPGA/IC synthesis can also be used to spotlight any RTL considerations with regard to synthesis.
3.3.4 Revision handle
Revision handle is quintessential to the idea of design reuse and ensures important guidance is not misplaced all over the design section. Revision manage and file management is above all important all through RTL coding as any code lost during this stage can severely affect the basic design timeline. To help control data, engineers use source handle administration systems. These are usually bundled with the Linux working methods or attainable from GNU (RCS, CVS, Subversion). These code management programs provide a complete historical past of each file as separate models.
three.3.5 malicious program upkeep
dealing with bugs is an important consideration for any design framework. it's average to discover purposeful irregularities within the design and their prevalence does not reflect the capabilities of hardware designers. as soon as a problem is recognized, it must be resolved. All design groups want a technique for tracking issues and guaranteeing their decision. The authors proposed retaining a trojan horse record for any design linked considerations.
three.4 Verification and Validation ambiance
The verification part is essential to supplying first time working silicon. Their verification methodology uses a twin song method. Verification happens at the module stage and additionally at the SoC system level. The Module Verification ambiance (MVE) functionally validates the core and ensures all design traits had been comprehensively verified. The SoC Verification ambiance (SVE) assessments the cores’ habits at the device stage and in particular assessments the connectivity between the core interfaces. An FPGA/ASIC design verification strategy turned into used to validate the assignment on the gadget SoC stage.
3.4.1 Module Verification ambiance (MVE)
an essential a part of the MVE become the era of the APB Bus functional model (BFM) to generate the practical behavior of the equipment bus. all the peripherals were in line with this standardized bus architecture and this enabled the use of a everyday mannequin to check the bus interface and registers contained within the peripherals. This mannequin further supplied a simple to use test ambiance. The diagram in figure 7 illustrates this. The BFM utilized Verilog projects for read/write accesses, including wait state control and was reused in all of the peripheral test environments. The BFM became beneficial for running assessments to obtain self belief in the functional conduct and for targeting high code insurance.
determine 7: APB Bus practical model
3.four.2 SoC Verification environment (SVE)
The SVE consisted of a separate however an identical examine answer for FPGA prototyping and the ASIC system stage verification. The FPGA solution was advantageous for mapping the finished SoC RTL code to include the CPU, debugger and all of the peripherals onto a FPGA. determine eight illustrates the basic structure implemented onto the FPGA machine.
figure 8: FPGA Prototype Validation
The CPU and different leading peripherals are related together as a single platform and tests were developed in R8051 CPU core program code to function the peripheral tests. The ASIC verification environment is comparable to the FPGA verify bed, apart from during this case all tests were run using RTL and technique particular gate-level stimulations. each and every of the peripheral firmware checks developed for the FPGA prototyping have been reused at ASIC device degree.
four. results and Conclusions
The task aim was to implement a SoC design framework for the birth of reusable IP. The selected normal equipment bus aided the building of plug and play peripherals that will also be reused in lots of other SoC purposes. The development of the 8051 CPU external facts bus to gadget bus-bridge offered for a standardized interface and simplified the peripheral development.
The design flows of Figures 4 and 5 were followed to be certain a consistent design method for the construction and equivalent guide for business general EDA equipment. The listing structure as defined in part 3.2 become also vital for associating files with each stage of the IC construction and preserving a smartly-managed database. each and every of the carried out IP blocks follows this accepted database constitution and this ensures reusability going forward. Design experiences ensured confidence and nice of the IP block design. The Verilog code became reviewed to make sure revision control and RTL coding instructions have been adhered to. a similar overview turned into conducted to make certain the verification environments at module and equipment level were acceptable to test the performance of these designs. The RTL become validated on a FPGA equipment and exams have been carried out at the gadget degree to look at various the peripherals connected to the 8051 CPU.
The IP framework as discussed in this paper is correct for implementation in an educational centre wishing to carry out a reusable IP programme. this technique and reuse ideas are generic in trade, but because of funding and aid constraints, may additionally not always be handy to install in an tutorial ambiance. This paper discusses the implementation of IP development for decrease bandwidth peripherals; nevertheless the underlying concepts of IP use and reuse are the same.
4.1 tutorial Centre Specifics
team of workers requirements for research are subsequently resourced from graduates pursing MEng and PhD levels. within the CSRC, workforce and academic researchers are chargeable for main initiatives and mentoring students. The graduates need advantage development to convey them as much as speed and having a structured development methodology makes it possible for deliverables to be met in a timely vogue. The advantages of IP capabilities retention was another excuse for introducing the IP construction framework, as work generated on tasks conducted in the past would had been problematic to development once postgraduates had achieved their analysis degrees. This became an important concern to get to the bottom of, as effective undertaking work carried out during the past might also had been unnecessarily misplaced.
four.2. Future techniques
The cores can be additional improved by offering a equipment C or C model as part of the developmental degrees to extra the level of abstraction and to speed up design verification and utility construction.
SystemVerilog is a hardware design and verification language with superior elements supposed to help clients boost reusable, transaction-stage, coverage-pushed testbenches. ideas reminiscent of assertion based Verification (ABV) may be utilized to the bus protocol to computer screen pin endeavor and the utility of insurance-driven tests add confidence in working silicon and supply an exhaustive trying out ambiance. These points introduce concepts of verification reuse.
Design for check (DfT) is often excluded from the design move in an academic atmosphere. DfT is a extremely crucial characteristic essential for IP reuse. The IEEE 1500 regular for Embedded Core verify (SECT) specifies a core wrapper design to accommodate DfT features. This IEEE 1500 compliant wrapper design may supply a valuable extension to the latest IP construction degrees.
The authors acknowledge the assist of the Circuits and methods analysis Centre (CSRC) in the electronic and computer Engineering (ECE) Dept. at the school of Limerick.
 Australian Microelectronics community, "IP design and Re-use," Jun, 2005.
 Freescale Semiconductor, "Semiconductor Reuse normal v3.2," Feb, 2005.
 VSIA Alliance, "VSIA structure document v1.0," Mar, 1997.
 P. Bricard, Jean-Pierre Gukguen, "applying the OpenMORE assessment software for IP Cores," in ISQED 2000: Synopsys, Mentor snap shots, March, 2000.
 J. Shandle, G. Martin, "Making embedded software reusable for SoCs," EETimes, Jan, 2002.
 J. Bergeron, "Writing Testbenches - practical Verificaton of HDL fashions", Kluwer tutorial Publishers, 2003.
 ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, may also 1999.
 IBM. CoreConnect Bus. architecture, "http://www-03.ibm.com/chips/items/coreconnect/."
 R. Herveille, "WISHBONE device-on-Chip (SoC) Interconnection structure for portable IP Cores," OpenCores company, Sep, 2002.
 D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.
 M. Kaskowitz, "bendy, specifications-based IP key," EETimes, Dec, 2002.
 Europractice, "http://www.msc.rl.ac.uk/europractice,"
 QualCore logic, "QualCore SoC circulation."
 V. P. Nelson, "VLSI/FPGA Design and check CAD tool move in Mentor pictures," Feb 15, 2006.