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constructing a Reusable IP Platform inside a equipment-on-Chip Design Framework targeted against an academic R&D environment | M9550-752 test dumps and PDF Download

by way of Brendan Mullane and Ciaran MacNamee,Circuits and gadget analysis Centre (CSRC),tuition of Limerick, Limerick, eire


A key challenge dealing with the semiconductor business is to mix intellectual Property (IP) from a lot of sources directly and successfully. Design times are at all times pressurized through time to market necessities and extending complexity. Industrial practices for developing system-on-Chip (SoC) IP have evolved below these pressures, however making use of these practices in an educational atmosphere presents additional challenges. The conception for constructing a framework for producing IP turned into in accordance with this reuse revolution and the benefits it brings to R&D. The skill to design high first-rate IP and to enable work practices for reuse methodology helps to achieve working SoCs in a well timed and efficient manner. This paper describes a strategy for imposing IP reuse practices perfect to an tutorial ambiance.

1. Introduction

quite a lot of elements are vital for efficient IP use, flexibility of integration, more advantageous ease-of-use, minimized can charge, and decent work practices for constructing IP. This paper is based on precise work developing an ASIC the usage of 0.35ìm method expertise. The structure in this IC is similar to SoC designs that use an eight-bit CPU and associated peripherals. it is shown that the framework for IP building established all the way through this task can be sure a hit deployment of both existing and new designs in future projects.

The present style in SoC design is to make use of latest IP as lots as viable. IP within the form of CPUs, DSPs and controllers, are being reused in new IC tasks at semiconductor systems design residences. Engineering groups now design chips with thousands and thousands of gates in lower than a year. only in the near past, such productivity would had been impossible, even unthinkable with out hardware IP reuse. Most academic environments do not need the supplies and infrastructure to permit such engineering capacity, however the underlying ideas of reuse can also be applied to permit more useful IP technology and potential retention for advantageous R&D.

This paper introduces a group of instructions and a methodology used to make sure a consistent strategy to designing IP and to permit for reuse of those modules in future tasks. the first stage become to investigate greatest industrial follow. Work describing the ASIC building cycle and its have an impact on on IP technology turned into carried out. a group of specifications for guaranteeing IP nice and ease of integration changed into additionally prepared. A key objective changed into to make certain expertise may well be retained inside the university centre to keep in mind anticipated graduate turnover.

2. IP Reuse Framework in CSRC

A assessment of the common issues in design use and reuse become initiated [1]. quite a few IP requirements were reviewed and these included Freescale’s Semiconductor Reuse regular [2], VSI Alliance’s set of necessities for establishing SoCs [3] and OpenMORE [4]. IP reuse could on no account have came about devoid of standards or with out the underlying infrastructure [5]. Design and verification reuse, a truth of lifestyles these days for most SoC designs, ensures the productiveness hole is stored manageable[6]. Design reuse considered an easy concept that can also be effortlessly adopted, has persevered to be complex in apply. problems exist in getting engineers to believe that reusable IP will work every time it's used in an IC. providing IP support capabilities and adoption of a correct verification technique develops this trust.

2.1 SoC structure and Infrastructure

The intention of this task was to establish a design methodology for generating IP. The methodology worried architectural selections and selection of design-flows for IP construction accompanied with the aid of the prerequisite IC design equipment. venture criteria such as the SoC structure, third-celebration core use, in-house IP development and the system bus interface had been all considered before the IC architecture was concluded and the peripheral integration was conducted. The simple SoC architectural diagram is proven in determine 1 and the comprehensive chip was taken via verification and the lower back-end ranges of synthesis, design, static timing analysis and closing design rule checking.

determine 1: SoC Design architecture

the following key choices have been made in relation to the IP help structure.

2.1.1 Peripheral Bus Interface

The preference of a standard SoC gadget bus for connecting the CPU to the equipment peripherals was vital to the objectives of this assignment. the usage of a standardized bus architecture is standard to constructing reusable IP. numerous bus requisites were investigated for the wants of the CSRC IC tasks. The 8051 CPU changed into used during this design and besides the fact that children the interior special function Register (SFR) bus became considered, the authors wished to make use of a common bus design to be reused in other IC implementations.

most of the foremost IC and IP groups base their IP portfolio development round a single SoC bus architecture. Semiconductor agencies equivalent to ARM and LSI logic use the open source AMBATM [7] bus regular. IBM uses its own proprietary CoreConnectTM [8] bus usual. The OpenCores initiative uses the WishboneTM [9] described bus interface. The authors observed that the AMBA bus structure was smartly supported amongst the IP provider community. This huge acceptance arises from the supply of an open bus standard that's license free and well proven in current SoC designs. clients have a excessive degree of self assurance picking IP it really is considered provider impartial. moreover, the AMBA bus is well supported through EDA groups providing verification aid. The AMBA bus changed into chosen because the bus interface for CSRC SoC tasks for these motives.

The AMBA bus enables partitioning for modular designs[10]. Its methodology for embedded processor design encourages both a modular and first time right equipment design. It additionally accelerates product migration by means of aiding module reuse. In selected, the AMBA APB bus specifies a versatile interface and small overhead support for low bandwidth peripherals. The IP design the usage of the AMBA interface is made less demanding by means of partitioning the excessive-conclusion and low-conclusion contraptions in the system and helps energy effective designs. all of the peripherals during this design used the AMBA - superior Peripheral Bus (APB) because the standardized interface. The CPU as a single bus grasp turned into interfaced to all of the peripherals via an in-condominium designed AMBA bridge interface.

The merits of using a typical bus interface for core building are smartly documented [1, 10, 11]. A demo AMBA APB register module, shown in figure 2, was helpful for demonstrating the desired interface design to postgraduates. The RTL code for this module helped the team to take into account the ideas of decent coding follow to consist of parameterization and tested the use of revision control for code alterations and malicious program fixes. all of the IP developed during this IC mission may also be reused in any other AMBA based mostly SoC applications and this aids future product and platform building

determine 2: pattern APB module

2.1.2 third birthday celebration Core Licensing

one more huge project turned into to designate an appropriate microcontroller for the task. The IP group turned into approached with regard to licensing of the CPU and debug cores. there have been a couple of features to licensing IP cores from an academic viewpoint. It was elementary to be certain a licensing association become made using a non-business research- licensing model. Many providers have been only prepared to license their cores in line with a full business association and the expenses quoted had been beyond an tutorial analysis budget. Some providers have been inclined to consider a decreased non-business license charge with the re-introduction of full expenses supplied the IC proceeds to commercial utility. other IP carriers restricted their set of deliverables to FPGA netlist implementation simplest. This restrained their alternative of third birthday celebration CPU and debug cores. happily, some IP corporations had adventure dealing with academic cases and have been prepared to free up IP deliverables and support for non-industrial analysis activity at a reduced cost. The leading creator became capable of carry out a survey of suitable cores and got here to an settlement for the third party IP essential for the SoC venture.

2.1.three Design Flows

The ASIC design flow and digital Design Automation (EDA) device choice is a crucial component of a good IP framework. The option of tools should complement the design flows and help reusability of IP. The centre accesses tool units offered as academic programmes from the semiconductor EDA companies. The CSRC additionally has access to standard EDA equipment by means of the Europractice[12] application service scheme. Their FPGA and Digital design flows had been drawn up across the availability of these tools and to plot the SoC IP building and integration. These flows were valuable in choosing the distinctive levels concerned in the construction of IP and SoC designs. besides the digital design circulate, a circulation for FPGA prototyping became also added. The FPGA construction allows for an affordable design validation platform and provides confidence with the aid of making certain relevant behavior before closing tape-out. Digital IC Design stream

The digital design follows the basic ASIC implementation route. a couple of semiconductor business web sites and technical paper searches published the average design flow that exists for digital ASIC design [13], [14].

determine 3: Digital IC design movement

The design stream and tools preference as drawn up in determine 3 were tailored to tool availability and the choice of IC strategies provided by way of Europractice.

2.1.three.2 FPGA Design circulate

The FPGA move in figure four is very corresponding to the digital IC design circulation, however the design equipment to put in force and program a FPGA design are diverse. The assignment used the Xilinx design kits and tools made accessible by means of the Xilinx university Programme. They used Xilinx Spartan 2 and 3 boards to enforce the digital design points. The Xilinx ISE webpack is a collection of equipment that takes Verilog RTL code and runs it via synthesis, physical design to equipment configuration. The remaining bit file can then be downloaded to application the FPGA machine to examine the useful behavior of the digital design. FPGA verification recommendations and their magnitude in design validation and reuse are discussed later.

figure four: FPGA Design flow

2.2 CAD Infrastructure

The CAD infrastructure became more desirable to carry out SoC development inside the centre. The original constitution protected three low-grade UNIX servers for running the IC design tools and retaining mission statistics. A plan become initiated to upgrade the IT hardware needs. each and every of the person PCs have been put in with VMware Linux, enabling users to maintain their windows OS but extra importantly each computing device may use its personal CPU processing energy with Linux to carry improved performance. Two excessive power Linux mainframes, obtained for retaining the undertaking databases were also utilized as license servers for the supported EDA equipment. the new set-up provides the efficiency requirements to perform IC R&D inside the CSRC centre.

a further step changed into opting for the EDA equipment indispensable for IP construction. tools for verification and guaranteeing fine of RTL code had been no longer in vicinity. youngsters the usage of their Europractice membership, the centre had access to frequent EDA tools at a decreased cost. tools reminiscent of ModelSim for RTL verification and Leda for RTL evaluation had been obtained. The latest version of Design Compiler changed into additionally upgraded based on business necessities.

3. Design Methodology and IP reuse Implementation

application of reuse can pay off in terms of construction charge and time-to-market. This section summarizes the development milestones for a standard IP design. Defining the flow and associated design experiences helps assure a repeatable, high exceptional, and reusable block of peripheral IP. an additional advantage of a documented flow is that different design agencies can use this methodology to boost IP in an analogous approach; ensuring IP is constant in its implementation, integration flow, deliverables, and general best.

3.1 building Milestones

IP/SoC design milestones are essential to the beginning of working silicon and attaining a ‘appropriate first time’ policy. These milestones are markers placed down throughout the development part to manage and measure the design recreation and progress. These markers point out studies happening all over the crucial ranges of the design section from delivery to end. Milestones take place on the natural progression of the challenge. figure 5 and desk 1 describe the sign-off milestones to consist of all most important design reviews.

figure 5: IP building Milestones

desk 1: IP construction tiers

degreeReview Description FSR useful Spec evaluate purposeful specification is complete, details on effort estimation, work breakdown constitution and agenda. DSR Design beginning assessment Design delivery, working towards, RTL coding & synthesis checklistTPR test Plan assessment comprehensive specification of verification atmosphere, examine situations, bus-models, transactors. RCR RTL Code evaluate RTL trojan horse fixes identified via exhaustive verification & RTL Lint/code checking TLR Trial design evaluation set up floorplan and function P&R. Floorplan in response to module connectivity, resolve congestion and timing –study clocking FVR final Verification evaluation excessive precedence trying out accomplished. established bugs in the RTL are fastened. insurance analyzed. Low precedence testing ok. FDR closing Design evaluation evaluate integrity assessments (DRC, LVS) STA, check Vectors and remaining gate-stage verification with finished layout timing.

3.2 venture Database structure

A standardized listing constitution is a must have for IP reusability. an efficient and straightforward to use database structure ensures compatibility and consistency of peripheral design. IP development contains specification, coding and verification as key design levels. subsequently, many guide file codecs are required. IP protection is additionally a key thought in IP reuse. The capacity to log and retain song of design adjustments is vital to the universal exceptional of the design. determine 6 shows the CSRC listing structure to assist the IP development tiers.

determine 6: typical CSRC listing Database

three.3. Reuse guidelines

3.3.1 Specification reports

The design studies are tremendous when it comes to generating a framework for IP building and reuse. These stories aid documentation and confirm decent design practices.

three.3.2 functional Specification

This doc provides an in depth useful description of the module and is written in advance of the IP building. The FSR evaluate takes place to be sure all features of the peripheral functionality are lined. The specification can be used to birth the design and RTL coding. The purposeful specification must be up to date as a consequence with any extra points requirements. The CSRC uses a draft template document as a suggestion for producing functional block and IC design requirements.

three.three.three RTL Coding and evaluation

RTL building contains coding the peripheral in a hardware description language such as Verilog or VHDL. Verilog RTL become used and a set of coding instructions for the IP era turned into issued. This set of coding principles ensures consistency, coding fashion nice and offers for superior protection. The RCR is a high level evaluation of the RTL code to be certain it's stylistically suitable and maintainable. The intent is to double-determine the code excellent. The basis for this evaluation is the RCR checklist. RTL analysis is conducted the usage of Leda for crosschecking RTL code guidelines in opposition t the Reuse Methodology guide (RMM). initial FPGA/IC synthesis can even be used to spotlight any RTL issues with regard to synthesis.

3.3.four Revision control

Revision handle is indispensable to the thought of design reuse and ensures crucial counsel is not misplaced throughout the design part. Revision manage and file management is certainly crucial all the way through RTL coding as any code misplaced all through this stage can seriously affect the normal design timeline. To support manage data, engineers use source handle administration systems. These are customarily bundled with the Linux operating methods or available from GNU (RCS, CVS, Subversion). These code administration programs provide a complete historical past of each and every file as separate types.

3.three.5 trojan horse renovation

coping with bugs is a vital consideration for any design framework. it is normal to find practical irregularities within the design and their prevalence doesn't mirror the expertise of hardware designers. as soon as a problem is identified, it must be resolved. All design groups need a way for monitoring considerations and guaranteeing their resolution. The authors proposed keeping a malicious program document for any design related issues.

three.four Verification and Validation environment

The verification part is essential to supplying first time working silicon. Their verification methodology uses a twin music method. Verification happens at the module level and also on the SoC equipment stage. The Module Verification environment (MVE) functionally validates the core and ensures all design qualities had been comprehensively established. The SoC Verification ambiance (SVE) tests the cores’ behavior at the system stage and in certain assessments the connectivity between the core interfaces. An FPGA/ASIC design verification strategy was used to validate the undertaking at the device SoC degree.

3.four.1 Module Verification ambiance (MVE)

an essential a part of the MVE changed into the technology of the APB Bus useful model (BFM) to generate the practical habits of the gadget bus. the entire peripherals were in response to this standardized bus structure and this enabled the use of a everyday model to verify the bus interface and registers contained inside the peripherals. This model extra provided a straightforward to use check ambiance. The diagram in determine 7 illustrates this. The BFM utilized Verilog tasks for study/write accesses, together with wait state control and changed into reused in all of the peripheral examine environments. The BFM become beneficial for operating tests to obtain self belief in the purposeful behavior and for targeting high code insurance.

determine 7: APB Bus functional mannequin

3.4.2 SoC Verification environment (SVE)

The SVE consisted of a separate but similar verify solution for FPGA prototyping and the ASIC equipment level verification. The FPGA solution become valuable for mapping the complete SoC RTL code to include the CPU, debugger and the entire peripherals onto a FPGA. figure eight illustrates the simple structure carried out onto the FPGA device.

determine 8: FPGA Prototype Validation

The CPU and different main peripherals are connected together as a single platform and exams were developed in R8051 CPU core program code to function the peripheral checks. The ASIC verification atmosphere is comparable to the FPGA look at various bed, except during this case all assessments had been run the usage of RTL and technique selected gate-stage stimulations. each of the peripheral firmware assessments developed for the FPGA prototyping were reused at ASIC gadget level.

four. effects and Conclusions

The challenge purpose turned into to put into effect a SoC design framework for the birth of reusable IP. The chosen standard system bus aided the development of plug and play peripherals that will also be reused in many different SoC purposes. The construction of the 8051 CPU exterior statistics bus to equipment bus-bridge offered for a standardized interface and simplified the peripheral construction.

The design flows of Figures 4 and 5 had been adopted to be sure a consistent design method for the construction and equivalent aid for industry typical EDA tools. The directory structure as explained in section three.2 was additionally critical for associating information with every stage of the IC development and maintaining a well-managed database. each and every of the carried out IP blocks follows this widely wide-spread database constitution and this ensures reusability going forward. Design reports ensured self assurance and first-class of the IP block design. The Verilog code changed into reviewed to make certain revision handle and RTL coding guidelines had been adhered to. an analogous review changed into performed to ensure the verification environments at module and device level have been appropriate to verify the functionality of those designs. The RTL was validated on a FPGA device and assessments have been carried out on the system level to look at various the peripherals related to the 8051 CPU.

The IP framework as discussed in this paper is correct for implementation in an academic centre wishing to carry out a reusable IP programme. this system and reuse concepts are general in industry, however because of funding and resource constraints, may additionally no longer at all times be easy to set up in an academic ambiance. This paper discusses the implementation of IP building for lessen bandwidth peripherals; however the underlying ideas of IP use and reuse are the identical.

four.1 educational Centre Specifics

team of workers requirements for analysis are subsequently resourced from graduates pursing MEng and PhD levels. in the CSRC, personnel and academic researchers are answerable for main initiatives and mentoring college students. The graduates want abilities building to deliver them as much as speed and having a structured construction methodology makes it possible for deliverables to be met in a timely style. The advantages of IP competencies retention become another excuse for introducing the IP development framework, as work generated on initiatives carried out during the past would have been intricate to development as soon as postgraduates had achieved their research degrees. This changed into an important concern to unravel, as valuable challenge work conducted in the past may also were unnecessarily lost.

four.2. Future techniques

The cores can be further more advantageous via featuring a device C or C mannequin as part of the developmental degrees to additional the stage of abstraction and to pace up design verification and application development.

SystemVerilog is a hardware design and verification language with superior facets meant to assist clients enhance reusable, transaction-stage, coverage-pushed testbenches. techniques corresponding to fact based Verification (ABV) may well be utilized to the bus protocol to display screen pin recreation and the utility of coverage-driven tests add self belief in working silicon and provide an exhaustive checking out atmosphere. These facets introduce concepts of verification reuse.

Design for look at various (DfT) is often excluded from the design circulate in an educational atmosphere. DfT is a extremely crucial characteristic needed for IP reuse. The IEEE 1500 common for Embedded Core check (SECT) specifies a core wrapper design to accommodate DfT points. This IEEE 1500 compliant wrapper design may supply a valuable extension to the latest IP development ranges.

5. Acknowledgements

The authors renowned the guide of the Circuits and techniques research Centre (CSRC) within the digital and laptop Engineering (ECE) Dept. on the tuition of Limerick.

6. References

[1] Australian Microelectronics community, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse common v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA architecture document v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "making use of the OpenMORE assessment program for IP Cores," in ISQED 2000: Synopsys, Mentor snap shots, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded utility reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - practical Verificaton of HDL fashions", Kluwer educational Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, might also 1999.

[8] IBM. CoreConnect Bus. structure, "http://www-03.ibm.com/chips/products/coreconnect/."

[9] R. Herveille, "WISHBONE device-on-Chip (SoC) Interconnection architecture for transportable IP Cores," OpenCores firm, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "bendy, necessities-based IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore good judgment, "QualCore SoC move."

[14] V. P. Nelson, "VLSI/FPGA Design and test CAD tool move in Mentor graphics," Feb 15, 2006.

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